6-52
1. Set up the test scope as per Step 1 of the 2110 troubleshooting procedure.
If test
=
FAIL then look for failure using the following steps:
Troubleshooting Procedure:
WDREG also drives the GPIB LEDS on the front panel. Bit patterns xxxxxOOOto xxxxx111 are sent in
a binary sequence with a 50 ms delay between patterns. The register is then reset to entry values.
WDREG U754 pin 19 (DIAG2) is then set to 1xxxxxxx and PMISCIN U854 pin 5 (bit D6) is tested for
1. If the test fails, the test result is set to FAIL.
WDREG U754 pin 19 (DIAG2) is set to Oxxxxxxx and PMISCIN A12U854 pin 5 (bit D6) (schematic
diagram 1) is tested for O.The test result is to PASS or FAIL accordingly.
Testing Method
Diagnostic Bit 2 Word Trigger Register A12U754 (diagram 20):
2170
DIAG2
3. Check that U550 pin 10 has a HI-to-LO transition on the first enable and a LO-to-HI transition
after the second clock pulse goes LO-to-HI. If bad, change U550; if good, check chip enable at
U854 pins 1 and 19 is LO after U550 pin 10 goes from LO-to-HI. If ok, then suspect U854. If the
enable is defective, troubleshoot and correct the problem.
2. Run test 2160 in CONTINUOUS mode and check that U550 pin 1 (COMREG) is set LO during the
period that the clock to U550 pin 9 (WRR) has a LO-to-HI transition. This may be done by saving
the COMREG signal in REF1 and displaying while acquiring the clock pulse on U550 pin 9. If these
signals are not coincident, then troubleshoot the cause.
Now using CH2 probe:
1. Set up the test scope as per Step 1 of the 2110 troubleshooting procedure.
If test
=
FAIL then look for failure using the following steps:
Troubleshooting Procedure:
Then pin 10 of U550 is set HI, and U854 pin 14 is tested for a HI. If test fails, the test result is set to
FAIL.
A BUSTAKE is executed (previously tested) and pin 10 of Interrupt Latch U550 is set LO. Then pin 14
(bit 2) of PMISCIN register U854 (schematic diagram 1) is tested for a LO, and the test results are set
accordingly.
Testing Method:
Waveform ILPDone A12U550 (schematic diagram 2):
2160
WPDN
3. Check that U550 pin 15 has a LO-to-HI transition after the second clock pulse goes LO-to-HI. If
no transition, change U550; if ok, check chip enable of U542 on pin 1 (SSREG) to be LO after
WRR on U550 pin 9 goes LO-to-HI. If ok, then suspect U550. If the enable is defective, trouble-
shoot and correct the problem.
Table 6-6
(cont)
Maintenance-2430 Service
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