6-51
Figure 6-8. Typical Register test waveforms.
4917-31
PIN 13
WD3
TEST
(
I
2150
COMREG
U550
PIN 15
In
~
~
PIN 1
COMREG
PIN
9
WRR
2. Run test 2150 in CONTINUOUS mode and check that U550 pin 1 (COMREG) is set LO during the
period that the clock line (WWR) to U550 at pin 9 has a LO-to-HI transition. This may be done by
saving the COMREG signal in REF1 and displaying it at the same time as the clock pulse on U550
pin 9 is acquired. If these signals are not coincident, then troubleshoot the cause and correct the
problem. See Figure 6-8 for typical register test waveforms.
1. Set up the test scope as per Step 1 of the 2110 troubleshooting procedure.
Now using CH 2 probe:
If test
=
FAIL then look for failure using the following steps:
Troubleshooting Procedure:
Pin 15 of U550 is then set HI and SSREG bits 0 and 1 are tested for HI. If the test fails, the test result
is set to FAIL.
NOTE
The inputs of U542 (pins 2 and 4) are wired together.
A BUSTAKE is executed (previously tested) and the 4Q output of U550 (pin 15) is set LO. SSREG
U542 bits 0 and 1 (pins 16 and 18) are then tested to see if they are LO, and the test results are set
accordingly.
Testing Method:
Interrupt Latch (COMREG) A12U550 and Display Status Register (SSREG) A12U542 (schematic
diagram 2):
2150
COMREG
Table
6-6
(cont)
Maintenance-2430 Service
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