A/D Converter and Acquisition Latches
(diagram 15)
AID CONVERTER. The combined samples of analog
signals are converted to eight-bit data bytes by the A/D
Converter. In Envelope Mode, the data bytes are applied
to two magnitude comparators, along with the previous
maximum and minimum data bytes to determine if it is
greater in magnitude than the last maximum or minimum.
If a new data byte is greater, the new data byte is latched
into the Acquisition Latches; otherwise, latching does not
occur. Clocking to direct the signals into the Acquisition
CCD Output (diagram 14)
The differential signals from both sides and both chan-
nels of the CCD arrays are combined and multiplexed onto
a single data line to the AID Converter. The output clock-
ing is referenced to the sample and phase clocks to main-
tain the correct data timing relationships of the samples.
Waveform data samples are therefore stored in the correct
Acquisition Memory locations after being digitized.
CCD/CLOCK DRIVERS. The CCDs are fast analog shift
registers that can hold more that enough samples to fill
the complete waveform record of 1024 samples per chan-
nel. The extra samples are used to account for the uncer-
tainty of the trigger point location in the 32 samples stored
in the input register. Once a trigger occurs, the samples
not needed to fill the waveform records are basically dis-
carded. For fast signals, waveform samples are stored
very rapidly and then shifted out at a rate that can be han-
dled by the AID Converter. When the sample rate is slow
enough to allow direct conversion of the input samples, a
Short Pipeline mode is used to shift samples directly
through the CCD registers. The Clock Driver portion of the
devices produces the phase clocks that shift the analog
data through the CCD registers. Other clocks used to
sample the signal and transfer the samples into and out of
the CCD arrays are generated in the CCD Clock and Sys-
tem Clock circuits (diagrams 11 and 7 respectively).
Common-mode adjust circuitry on the output of the
Peak Detectors is used to control the overall gain of the
Peak Detector/CCD acquisition SUbsystem. Using digital
signals to the DAC system, analog voltages are generated
that set the gain of the Common-mode adjust amplifiers.
These amplifiers monitor the dc common-mode level of the
Peak Detector outputs and match it to the control gain
level set by the System J.LP.That dc level sets the CCD
signal gain.
3-2
Peak Detectors and CCD/Clock Drivers
(diagram 10)
PEAK DETECTORS. Additional buffering of the signal
to the CCDs is provided by the Peak Detectors for all
acquisition modes. The bandwidth of the input amplifiers of
the Peak Detectors is switchable for FULL, 50 MHz, and
20 MHz bandwidths. In Envelope acquisition mode, dual
min-max Peak Detectors detect and hold the minimum and
maximum peak signal amplitudes that occur between sam-
pling clocks. Those min and max signal values are then
applied to the CCDs for sampling. Control data from the
System IlP controls the bandwidth selection, and peak
detector clock signals multiplex the signal samples from
the Peak Detectors to the CCDs. A calibration signal input
is provided to the Peak Detectors for use in automatic cali-
bration and diagnostic testing of the acquisition system.
PREAMPLIFIERS. The Preamplifiers provide switchable
gain setting and buffering of the attenuated input signal.
Single-ended input signals are converted to double-ended
(differential) output signals. Variable Vertical Mode gain,
vertical position, and DC Balance are controlled by input
signals to the Preamplifiers. The System J.LP-controlled
gain in combination with the switchable attenuator settings
allow the complete range of available VOLTS/DIV switch
settings from 2 mV to 5 V to be obtained. Trigger pickoffs
provide a sample of the input signal to the trigger system
for use as a triggering signal source. With the Video
Option installed, a Channel 2 pickoff signal is supplied
from the Preamplifiers as a trigger signal source. Also, a
Channel 2 Offset signal used to control the back-porch
clamping is provided from the Video Option to the Chan-
nel 2 Preamplifier.
Attenuators and Preamplifiers (diagram 9)
ATTENUATORS. The Attenuators are settable to 1X,
10X, or 100X attenuation, to reduce the input signal level
to within the dynamic range of the Preamplifiers. Input
coupling for the signal to the Attenuators may be either
AC or DC with 1 MI1termination or DC with 50 11termina-
tion. Attenuator and coupling switching are controlled by
the System J.LPusing register-activated magnetic-latch
switches.
This discussion is of the block diagram shown in
Figure 3-1.
SIMPLIFIED BLOCK DIAGRAM DESCRIPTION
Theory of Operation-2430 Service
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