Display Output (diagram 18)
Horizontal and vertical signal current from the Display
Controller are converted into the deflection voltage signals
used to drive the crt deflection plates by the Display Out-
put circuitry. Vector generation circuitry provides a choice
of either connected waveform dots (vectors on) or a dots-
only waveform display. Display switching circuitry connects
the correct deflection signals to the vertical and horizontal
output amplifier for YT (vertical signal versus time), XY
Display Controller (diagram 17)
The Display Control System controls the display of the
waveforms and readouts. Data bytes stored in the Display
Memory are read out and D-to-A converted into vertical
and horizontal current signals used to generate the
waveform dots and readout characters. State-machine
circuitry under control of the System /otPperforms all the
display tasks assigned including control of the Z-Axis. The
System /otPand the Waveform /otPare therefore free to
carryon with other functions until it becomes necessary to
make a display change (such as a menu or display mode
change or a waveform data update). Display state-machine
clocks are generated from the Time Base Controller
5 MHz clock signal.
Display and Attributes Memory (diagram 16)
The 512 data points to be displayed out of the 1024
data-point record are transferred to the Display Memory
from the Waveform /otPSave Memory after any required
processing such as adding, subtracting, multiplying, or
interpolating is done. Subsequent refreshes of the display
are then continually made from data stored in the Display
Memory, and that memory is only updated as necessary
to display different waveforms or portions of the waveform
record (a new horizontal position or new waveform called
up for display). The Attributes Memory holds all the
VOLTS/DIV and SEC/DIV scale factors for each of the
waveforms displayed. Readouts of that data are also
displayed on the crt. Waveform data to the XY Plotter is
obtained directly from the Display Memory and only 512
data points for each waveform are available to be plotted.
The Bus Connect circuitry includes logic gating that
arbitrates when the Waveform /otPmemory space (RAM)
and addressable devices are under control of the System
/otP.The System /otPmay gain control by a BUS REQUEST
to which the Waveform /otPissues a BUS GRANT signal;
or if the Waveform /otPis held reset, the System /otPissues
a BUSTAKE signal. The BUSTAKE is used when the Sys-
tem /otPwrites a waveform display task list into the
Waveform /otPCommand RAM space. When the reset is
then removed from the Waveform /otP, it does all the
waveform data processing tasks given to it to do by the
System /otPwithout further need of System /otPaction.
3-4
Waveform Processor (diagram 2)
The Waveform Processor performs the high-speed
data-handling operations required to produce and update
the crt displays. Waveform data is transferred from the
Acquisition Memory to a "Save" Memory in the Waveform
/otPwork space. Waveforms may be digitally added, multi-
plied, or averaged, as part of the display processing that
the Waveform Processor does before transferring the data
to the Display Memory. The Save Memory is kept alive
during periods of power-off by the stored charge on a
"super cap." This short-term storage holds the Save
waveforms, the reference waveforms and/or front-panel
setups for a period of three to five days (nominal). The
Waveform /otP memory space and all devices on the
Waveform /otPaddress bus are addressable by the System
/otPvia the Bus Connect circuitry for I/O operations.
TIME BASE CONTROLLER. The Time Base Controller,
under direction of the System JotP,monitors and controls
the acquisition functions. When the pretrigger samples are
obtained, the digitization process is started. Samples are
counted to store the correct number in the Acquisition
Memory, and the trigger point is properly located in the
waveform record. Among the various tasks done by the
Time Base Controller, Clock signals generated by the Time
Base Controller provide the acquisition rate, the calibrator
frequency, and enable the Trigger circuitry to accept a
trigger after the pretrigger data is acquired.
Time Base Controller and Acquisition Memory
(diagram 8)
ACQUISITION MEMORY. Digitized waveform data
bytes are transferred from the Acquisition Latches to the
Acquisition Memory under control of the Time Base Con-
troller. The data is temporarily stored here before moving
to the Waveform Processor Save Memory under control of
the Waveform Processor.
ACQUISITION LATCHES. For Normal and Average
acquisitions, the data bytes are passed directly through
the Acquisition Latches to the Acquisition Memory where
they are stored temporarily before transfer to Waveform
Processor Data Bus and the Waveform Processor Save
Memory. The Envelope acquisition waveform bytes in the
Acquisition Latches are the maximum and minimum data
point values that occurred in the sampling interval. When
the SEC/DIV setting reaches the maximum sampling rate,
only one min-max pair is present during a sampling inter-
val; and, in that case, the Envelope data byte comparisons
are done by a firmware routine as the data is transferred
from the Save Memory to the Display Memory.
Latches comes from the System Clock circuit and is refer-
enced to the Output Clocks to maintain the correct data
input to the magnitude comparators for making the
Envelope min-max comparisons.
Theory of Operation-2430 Service
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