3-11
3. The first CH 2 output is then ungated, and the
second CH 1 Sample-and-Hold output and the second
CH 2 Sample-and-Hold output are gated on in succes-
sion to couple their held levels to the A/D Converter.
This multiplexing process continues until 512 samples
from both sides of the two CCDs have been converted.
2. While the output level of the first CH 1 Sample-
and-Hold is gated to the A/D Converter, a CCD Output
Sample clock gates the outputs of the CH 2 Single-
Ended Amplifiers to their corresponding CH 2 Sample-
and-Hold circuits. Both the first CH 1 Sample-and-Hold
outputs and the inputs to the CH 2 Sample-and-Hold
circuit are then ungated, and the first CH 2 Sample-
and-Hold output circuit is gated on to pass its held sig-
nal level to the AID Converter.
1. A CCD Output Sample clock gates the outputs of
both CH 1 Single-Ended amplifiers to the input of their
associated Sample-and-Hold circuit. There, the input
levels are sampled, and the gating is then disabled to
hold the sampled level on the Hold capacitors. One of
the CH 1 Sample-and-Hold output circuits is then gated
on to pass the sample level to the A/D Converter for
digitization.
The CCD Data Clocks and the CCD Output Sample
Clocks (diagram 7) control the timing between when the
signals are coupled to their corresponding Sample-and-
Hold circuits and when the Sample-and-Hold circuit out-
puts are coupled to the single analog input of the A/D
Converter (diagram 15). Briefly for FISO mode, the timing
is as follows:
Both pairs of the differential output signals from the
CH 1 and CH 2 CCDs are applied to the inputs of the
corresponding pairs of Single-Ending Amplifiers
(diagram 14). Each amplifier converts the differential signal
clocked to its inputs to a single-ended output signal. That
signal is used to drive the input of a corresponding
Sample-and-Hold circuit (also shown on diagram 14).
ANALOG DATA CONDITIONING
AND AID CONVERSION
The remainder of the Short-Pipeline save operation is
similar to a FISO save. The Acquisition Memory Address
Counter is incremented by the clock that writes data to
the memory as in FISO, but at the synthesized rate rather
than at the 2 MHz FISO rate. As in FISO, the Trigger
Location information is used to determine the trigger point
location. Enough samples are saved into memory after the
trigger point is found to fill the post-trigger requirements
before turning control over to the Waveform j.LP.
Theory of Operation-2430 Service
Short-Pipeline Mode
For Short-Pipeline mode, the Time Base Controller gen-
erates an enabling clock that controls the 2 MHz write
clock to the Acquisition Memory. The correct enabling rate
of the SAVEACQ write clock for the selected SECIDIV
setting is synthesized within the Time Base Controller,
using a CCD Data Clock input to
obtain
the base fre-
quency. This enabling clock turns on the controlling gate
circuit to pass only two SAVEACQ clocks (via the Mode
Control Circuit) to write to the Acquisition Memory, saving
one digitized data point per channel (two in Envelope
Mode-one max and one min per channel). Then the syn-
thesized clock from the Time Base Controller disables the
SAVEACQ clock for a certain number of clock cycles.
Specifically, the number of ungated clock cycles equals the
SECIDIV setting divided by 50 j.LS,i.e., four clock cycles at
a SEC/DIV setting of 200 j.Ls. Therefore, the samples
saved in the Acquisition Memory in Short-Pipeline mode
produce a constant 50 samples per horizontal division
when displayed, regardless of the SEC/DIV setting.
As the samples are being moved into the Acquisition
Memory, the Time Base Controller monitors clocks from
the CCD Data Clock circuit to determine when the 1024
digitized samples (per each channel) are saved. The Time
Base Controller then stops writing to the Acquisition
Memory by disabling the write clock and switches control
of the memory to the Waveform j.LP(again, via the Memory
Mode Control circuit). The Time Base Controller then
strobes the Waveform j.LP(diagram 2) to signal that the
acquisition is complete and the waveform data is available
for processing and display.
The memory write clock also increments the Acquisition
Memory Address Counter to provide the address for writ-
ing the next data point into the Acquisition Memory. The
address is latched into the Record-End Latch during each
memory write so that the beginning of the acquisition
record can be determined when the Acquisition Memory is
accessed later.
To do a waveform save, the Time Base Controller is
selected to control writing into the Acquisition Memory via
the Memory Mode Control circuit (diagram 8). The
SAVEACQ clock circuitry is then enabled to pass a 2 MHz
clock signal (D24XPC) from the CCD Data Clock circuit
(diagram 7) to do the memory writes at the FISO rate.
not needed to fill the 1024-point waveform record have
been clocked out so that only the samples properly posi-
tioned around the trigger point remain in the CCD, the
Time Base Controller enables the save acquisition clocking
to begin moving the digitized samples from the A/D Con-
verter into the Acquisition Memory, thus saving the
waveform record. (See "Detailed Circuit Description" for
more trigger point location information.)
To Next Page
Loading...
