The Waveform ~P outputs (via its Address Latch)
addresses to the Address Counter for Acquisition Memory.
The Address Counter is held in its load mode by the
Waveform ~P (via the Memory Mode Control circuit), pass-
ing the address through to Acquisition Memory. The
Waveform ~P enables the Acquisition Memory and
provides the clocks (via the Memory Mode Control circuit)
to move stored data out to the Waveform Data bus via the
Data Bus buffer. This data is written either into the
When the Waveform ~P reads the acquisition done
(ACQDN) signal from the Time Base Controller, it writes
an address (via the Address Latch) which is decoded by
the Register Address Decoding circuit (diagram 2). The
decoded address signals the Record-End Latch
(diagram 8) to enable its contents (the last addressed
memory location for the stored acquisition) to the
Waveform ~P data bus to be read to determine the loca-
tion of the last record byte stored. The Waveform ~P then
uses that location to determine the location of any byte in
Acquisition Memory.
Data Transfer to SAVE Memory
Once the 1024 digitized signal bytes per channel are in
Acquisition Memory, the Time Base Controller ungates the
SAVEACQ clock and switches the the Memory Mode Con-
trol circuit to the Waveform ~P. It also signals the
Waveform ~P, via the Display Status Buffer (diagram 2),
that the acquisition is complete. The Waveform ~P can
then access the Acquisition Memory.
ACQUISITION PROCESSING
AND DISPLAY
The output of the AID Converter is fed to the Envelope
Min-Max Comparators (diagram 15). The outputs of the
Acquisition Latches are also fed back to those compara-
tors. Due to the previously described timing action of the
CCD Data Clocks, the newly digitized minimum or max-
imum value from the Peak Detectors (see "Input Signal
Conditioning and Analog Sampling") is compared to the
last value latched into the Acquisition Latch that
corresponds to the new point. If the newly acquired point
is outside the previous min or max value, the appropriate
Envelope Min-Max Comparator gates the 2 MHz clock,
and the new data byte is latched into the corresponding
acquisition latch.
bus in the following manner: CH 1 max, CH 2 max, CH 1
min, CH 2 min. This is the same order in which the analog
samples are clocked into the AID Converter.
3-12
For Envelope Mode, the Time Base Controller disables
continuous gating of the 2 MHz clock to the Acquisition
Latches. This action turns over the gating of that clock to
the Envelope Min-Max Comparators (diagram 15). With
the 2 MHz clock ungated, the CCD Data Clocks will con-
tinue to control the enabling of the outputs of the acquisi-
tion latches as described, but the new data bytes are not
continually clocked into the latches. The result is that only
the data bytes clocked in by the Envelope Min-Max Com-
parators are sequentially clocked to the Envelope Data
For Normal and Average Acquisition Modes, data is
clocked into the Acquisition Latches by the same 2 MHz
clock used by the AID Converter. Enabling of the outputs
of the Acquisition Latches is controlled by the CCD Data
clocks in a sequence that ensures that the data clocked
out from the enabled latch corresponds to the CCD side
and Sample-and-Hold circuit that provided it. The 8-bit
sample bytes are then saved in Acquisition memory in the
same order they were obtained. This "structured" method
for saving acquisitions keeps the data in the correct time
sequence for display.
The time-multiplexed signal is applied to the input of the
AID Converter Circuit for digitization. The System Clocks
circuit (diagram 7) provides a 2 MHz clock to the con-
verter, for a 2 MHz data-conversion rate of the input sig-
nal. The resulting digital output byte is applied in four 8-bit
bytes to the Acquisition Latches (diagram 15).
For Short-Pipeline sampling mode, the gating for the
inputs to the Sample-and-Hold circuits is the same as in
FISO mode. However, since only one side of each CCD is
used per channel, only one pair of differential outputs (per
CCD) and the corresponding Single-Ended Amplifier and
Sample-and-Hold circuits transfers valid waveform sam-
ples to the AID Converter. The Short-Pipeline mode save-
acquisition clocking ensures that only the valid converted
data is saved (see "Short-Pipeline Mode" in "Acquisition
Process and Control"). Observe, however, that the signal
to the AID Converter is still a 2 MHz time-multiplexed sig-
nal, but with invalid data half of the time. Since the invalid
data is, in effect, discarded by the Short-Pipeline Mode
save-acquisition clocking, the AID Converter continues to
operate at a constant 2 MHz conversion rate as in
FISO mode.
The samples are clocked through each side of the
CCO at a 500 kHz rate, resulting in an output sam-
pling rate of 1 MHz per channel. Also note that the
4-to-1 gating of the two channels and their respec-
tive outputs results in a
2
MHz time-multiplexed (4-
to-1) signal to the AID Converter.
NOTE
Theory of Operation-2430 Service
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