3-13
The differentialcurrent outputs from the Horizontal and
Vertical DACs are converted to single-endedvoltages at
the input to the Display Output circuitry. Those voltages
then drive either the correspondingHorizontaland Vertical
Vector Generators (diagram18) for vector displays or the
Horizontal and Vertical Output Amplifiers directly for dot
displays.
Data Display
Data, waveform or other, is converted to two comple-
mentary output currents by each Display DAC. These
currents are analog in nature, but reflect the
±
256-bit
resolution of the DACs. Therefore,the current outputs are
a series of discrete analog levels(or steps, if the current is
varying),each levelcorrespondingto the 8-bit byte applied
to the DAC.
It should be noted that the incrementingaddressessup-
plied via the address latch are also applied to the Ramp
Buffer. Since each incremental address corresponds
directly to the data byte it addresses,and since the output
of the Ramp Buffer (diagram16) will be converted to a
staircase waveform by the Horizontal DAC, the addresses
can provide the horizontal deflection (or "ramp") neces-
sary for YT displays.
The System I-lPuses data writes to the Mode-Control
Register (diagram17) to select which portion of the
Display Memory(Vertical,Horizontal,or Attribute) or which
register (Volts Cursors or Time Cursors) is selected for
output to the Vertical or Horizontal DACs. The System I-lP
also uses the Mode-Control Register to select, via the
Horizontal Data Buffers, whether the waveform data in the
Horizontal Ram is applied to the Horizontal or Vertical
DAC,allowingeither YT or XY displays.
Data Transfer to Display DACs
When the SystemI-lPinitiates the display of the data
stored in Display Memory, it writes (via its data bus) the
starting address of that data to the Display Counter
(diagram17). It also outputs an address that latches, via
the Register Select Circuit, the starting address into the
DisplayCounter. Simultaneously,data from the System I-lP
initiates, via the Display Control Register (diagram17), a
strobe to the Display State Machine. The Display State
Machine then signals the Address Multiplexer, gating the
address(es) output by the Display Counter through to
Display Memory (diagram16), and begins to gate a clock
from the DisplayClocks circuit to the DisplayCounter.The
Display Counter incrementsfor each (display)clock cycle,
accessingsuccessiveaddressesin Display Memory as the
SystemjJ-Pclocks the data out of DisplayMemory.
Theory of Operation-2430 Service
The Waveform I-lP addresses (in parallel) both the
Waveform Save Memory and the Display RAMs via the
Address Multiplexer(diagram17). The System I-lP gates
the address through to the Display Memory (the Vertical,
Horizontal, and Attribute RAMs on diagram 16) via the
Display Control Register (diagram17). The Waveform I-lP
then clocks the data out of its memory into the appropri-
ate DisplayRAM.
Data Transfer to Display Memory
Once an acquisition is stored in the Waveform Save
Memory, it must be moved to the proper locations in
Display Memory, from where it is converted back to an
analog signal for display. The WaveformI-lPupdates each
section of Display Memory at the proper time, based on
internal routines stored in Waveform Processor ROM and
timing suppliedby the SecondaryClocks via the Waveform
Processor Clock and Bus Grant Decoding circuit. The
Waveform I-lP also writes attribute changes (such as
changes in horizontal position) to the Display Memory
(whenassignedthe task by the SystemI-lP).
It should be noted that the Waveform Save Memory is
a paged RAM memory. The Waveform I-lP uses a paged
address scheme to load waveform datainto one of six
possible sections, depending on the source (CH 1 or CH 2)
or the destination (REF1, REF2, etc) of the waveform.
Observe also that the Waveform Save Memory RAMs are
supplied power by the Standby Circuit when instrument
power is off, allowing for preservation of the waveform
data stored in each of the six sections. See the "Detailed
Circuit Description" for more information concerning the
structuring of the Waveform Save Memory and operation
of the Standby Power circuit.
Most transfers from Acquisition Memory are straight
out of Acquisition Memory, through the Waveform Data
Buffer, and into a corresponding memory location in
Waveform Save Memory. However, the Waveform I-lP
sometimes disables the Waveform Data Buffer and reads
the data directly into its own internal register via the Data
Bus Buffer. The Waveform I-lP then processes it according
to tasks assigned by the System I-lP, using routines stored
in its own ROM. For instance, in Envelope mode the
Waveform I-lP will read (into a second internal register) the
corresponding byte stored in Waveform Save Memory
from the previous acquisition. If the new byte, stored in
the first internal register, is determined to be a new max or
min value, the Waveform I-lP uses it to replace the previ-
ous value in Waveform Save Memory.
Waveform Save Memory or into an internal register of the
Waveform I-lP for processing, depending on the display
requirements.
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