3-15
Address Buffers
Address Buffers U632 and U730 provide buffering of
the Systemf.LPaddress lines to the various addressable
devices. The buffer chips are permanently enabled and
provide both current buffering and electrical isolation for
the address lines. Test point TP840is provided as a
source of an oscilloscopetrigger signal when checkingthe
Moving test jumper J126 to its"KERNEL" position dis-
ables buffer U650 and forces it to its tri-state (high-
impedanceoutput) mode.The pull-up and pull-down resis-
tors on the data bus lines, R742, R746, and R744, place
an instruction byte on thef.LPdata bus that causes the f.LP
to repeatedly increment the addresses placed on its
address bus lines through their entire range. This pro-
cedure is a troubleshootingaid that exercises a good por-
tion of the address-decodingand chip-selectcircuitry.
Data Bus Buffer
Data Bus Buffer U650 provides buffering of the data
bus lines. It is bidirectionalto enabletwo-way communica-
tion between the System f.LPand the data bus. In normal
operation, jumper J126 will connect the chip-enablepin to
ground, and the buffer is enabled to transfer data. The
direction of the transfer is controlled by the R/W signal
from the Systemf.LPvia inverting buffer U572C.
The WR signal is derived from an inverted version of
the f.LPR/W signal (via U572C)with a bufferedf.LP
Q
signal
(via U880D) NANDed by U844B. The output of this
NAND-gateis a signal with a fallingedge that indicatesthe
start of a write cycle to the addresseddevice and a rising
edge that latches data from the f.LPinto the addressed
device. The
Q
signal is used here instead of HVMA (as
was used to generate RD to produce a data hold time of
more than 100 ns as needed by the oscilloscope Time
Base Controllercircuitry.
The RD signal is derived from U844A, which NANOs
the HVMA signal with the f.LPR/W signal. Inverting buffer
U572C provides added driving power to the R/W signal,
and inverting buffer U884B reinverts it back to its original
polarity before it is appliedto NAND-gateU844A.The out-
put of U844A is the RD signal, whose falling edge indi-
cates the start of a read cycle. The rising edge of RD is
coincidentwith the latchingof the data read into f.LPU640.
The E signal (U640 pin 34) and the
Q
signal (U640
pin 35) are ORed together by U840D to generate the
HVMA (Host Valid Memory Address) signal. When HVMA
at U840D pin 11 is HI, the address on the bus is valid.
Once the external circuitry receivesa valid address signal,
it proceedswith the specifiedmemory access. The signals
used throughout the 2430 to enable and time these
accessesare RD (read)and WR (write).
System f.LPU640 generates three signals used to con-
trol the communication activities of external circuitry. Of
these signals, E and
Q
are for timing purposes.The rising
edge of
Q
signals that the address on the bus is valid;
data to thef.LPis latchedon the fallingedgeof E. The third
signal generated is the R/W signal. It is valid the same
time the address is valid, and its state (LO or HI) deter-
mines whether an addresseddevice is written to or read
from.
System j.tP
System f.LPU640 executes instructions stored in the
System ROM in order to initiate and control the various
functions of the 2430. Internally, the microprocessor has
16-bit data paths; externally it has an 8-bit data bus for
communication and a separate 16-bit address bus. No
address/data bus demultiplexing is necessary. The f.LPis
driven by an external 8 MHz clock that is divided by four
internallyfor a 2 MHz cycle rate. The numberof cycles per
instruction varies from a minimumof 2 to a maximum of
20, with the average being about 4 cycles per instruction.
The f.LPexecutes,on the average,1/2 MIP (Million Instruc-
tions Per second).
The System Processorcircuitry alsocoordinates the
functions of the two other microprocessors in the 2430,
the WaveformProcessorand the Front PanelProcessor.
The System Processor(diagram 1) is the control center
of all operations in the 2430. It consists of an 8-bit
microprocessor (f.LP),an 8-bit data bus, a 16-bit address
bus, a prioritizing interrupt system, hardware address
decoding,"nonvolatile" and volatile RAM space,and 144K
bytes of bank-switchedROM.
SYSTEM PROCESSOR
DETAILED CIRCUIT DESCRIPTION
Theory of Operation-2430 Service
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