Interrupt Logic
The Interrupt Logic circuit provides a means by which
other SUb-systemsmay interrupt the normal program exe-
cution being done by the J.LPto request service.Three lev-
els of interrupts are available in J.LPU640. The NMI (non-
maskableinterrupt) that occurs at power-down has priority
On power-down, the PWRUP line is immediatelypulled
LO, and capacitor C938 begins discharging via R938 and
diode CR936. At the time this discharge is initiated, the
NMI (nonmaskableinterrupt) is asserted, and the proces-
sor branches to the power-down routine. In the power-
down period before the power suppliesare discharged,the
J.LPdoes the housekeepingactivities that ensure the data
stored in Nonvolatile(NV) RAM is correct and turns off any
asserted 50-ohm input coupling. After approximately
10 ms of discharging,the RESET line is asserted to hold
the J.LPreset while the power supplies finish their
discharge. If power to the System J.LPis not lost but
merely reduced,approximately260 ms after NMI goes LO,
the System J.LPwill fetch its reset vector and restart as
though the power was actually cycled off and then
back on.
The Power-Up Reset circuit consists of an RC-
integrator formed by R936 and C938 and a comparator
circuit formed by U940B and associated components.
Capacitor C938 begins charging when the PWRUP
(power-up) signal goes HI, and the comparator detects
when this charging level crosses a predefined threshold
voltage (set by R944, R943, and R942). Positive feedback
through R942 separates the turn-on and turn-off thresh-
olds of comparator U940B to ensure that switching of the
comparator is positive when the threshold levelis reached.
The turn-on circuit delay of approximately 100 ms allows
all electricalcomponentsto stabilizebefore attempting any
circuit operations.
Power-Up Reset
The Power-Up Reset circuit keeps the System J.LPreset
until all instrument power suppliesare sure to be operating
properly and for the 100 ms delay needed by J.LPU640.
This delay time is enough that the processor will beginthe
operating program with all electrical components in valid
(defined)states after the instrument is turned on.
BFFFh. The ROM selected depends on the states of the
three PAGE-BITS written to PC register U860. These
ROM select bits are initialized LO by the RESET signal
from the Power-Up Reset circuit when the oscilloscopeis
turned on.
3-16
When the J.LPneeds information from one of the other
System ROMs, it writes three bits of selectdata into regis-
ter U860. Of these bits, PAGE-BITOand PAGE-BIT1,
applied to 1-of-4 Decoder U890B, select which ROM chip
of ROMOis enabled.PAGE-BIT2is the most significantbit
of the ROM addresses and determineswhich page of the
enabledROM is addressed.The applied bit levels produce
a ROM select for one of the 32K ROM chips when data
selector U890B is enabledby U890A.This enablingoccurs
when an address between 8000h and BFFFhis output by
J.LPU640,causing U890Ato produceits ROMO.Xoutput to
U890B. Page switching in this way permits eight 16K-byte
pages of ROM to reside between addresses 8000h and
Immediately after the power-up reset ends, J.LPU640
automaticallytries to fetch the reset vector (the location of
the first program instruction)from locations FFFE(hex)and
FFFF(hex)in its address space. Anytime the System J.LP
tries to access memory, the HVMA (host valid memory
address)signal from U840Dwill be HI during the time the
address is guaranteed to be valid. Addresses FFFE and
FFFFhave bits AE and AF (the two MSBs of the address
bus) set HI; therefore, with the HVMA signal HI, NAND-
gate U870D outputs a LO that enables U890A, and a
ROM1 select output is obtained from U890A for both
addresses.The ROM1 applied to the chip-enableinput of
ROM U670, along with the LO RD applied to its output
enable, outputs the two 8-bit data bytes from location
FFFEand location FFFFonto the system data bus via bus
transceiver U660. The address contained in these bytes
directs the J.LPto the start of its program,and the program
is started.
System ROM
The System ROM (read-onlymemory) stores the com-
mands and data used by System J.LPU640 to execute its
control functions. The System ROM is made up of one
16K byte x 8-bit memory device, U670, that contains the
System J.LPoperatingsystem, and four page-switched,32K
byte x 8-bit memory devices, U680, U682, U690, and
U692 used for storage of all the additional operating rou-
tines. This gives a total of 144K bytes of ROM space.
Each ROM is individuallyenabled by the ROM Select cir-
cuitry, and the addresseddata will only appearon the sys-
tem data bus when the RD (read) signal goes LO. Since
J.LPU640 has the capability to address only 64K locations
and has to addressother things besidesROM,the System
ROM is split into nine pages. Address decoders U890A,
U890B, and part of PC Register U860, select the page of
ROM to be read from to allow the System J.LPto access
the entire 144K byte ROM space.
incrementing address lines in the forced"KERNEL"
troubleshooting mode described in the "Data Bus Buffer"
description.
Theory of Operation-2430 Service
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