3-17
A block of addressesfrom 6000hto SFFFhcorresponds
to the host memory-mappedinput/output (HMMIO) block.
Addresseswithin this block are decodedto produce a LO
HMMIO signal to 1-of-8 Decoder U884 and Octal buffer
U830. The three MSBs of the I/O address block and the
HVMA (host valid memory address)are decoded by AND-
gate U8S2 and inverter U866C to output a HI level for
addresses between 6000h and 7FFFh. This output is
NANDed by U870B with the inverted AC (address bit C)
line from U866A to decode the I/O addresses between
6000h and SFFFh.
To permit the System ILPto control the hardwarefunc-
tions of the 2430, several control registers have been
assignedto uniqueaddresseswithin the ILPaddressspace
(memory-mapped).These registers appear as blocks of
read-only,write-only, or read-write memory to the System
ILP. The data bits handled by these registers control
specific hardwarefunctions,and the commandswritten will
not violate any hardwarerestrictions.
The System Address Decode circuit generates specific
enables and clocks when certain addresses (or blocks of
addresses) appear on theILPaddress bus. Figure 3-2, a
simplifiedmemory map, illustrates the areas addressedby
blocks.
System Address Decode
Besides interrupt status, three other status bits are
read from the Interrupt Register.These are the DCOK (dc
ok) signalfrom the power supply (check during the calibra-
tion routine register checks), BUSGRANT from the
Waveformf.LP,and FPDNRD.DCOK signifiesthat the vari-
ous power supply voltages are within proper limits; BUS-
GRANT indicates that the Waveform ILPhas relinquished
bus control in its operating space and that those
addresses are now mapped into the System ILPaddress
space. FPDNRD indicates that the Front Panel ILP has
read the data sent to it from the System ILP.
When an IRQ interrupt is detected, the ILPexecutes a
read of location 6010h which is the address of Interrupt
Register U654 (an octal buffer). That address is decoded
by 1-of-8 Decoder U884 to set INTREG LO and enable
U654.The enabled buffer passes the status of the various
interrupt lines at its inputs to the data bus for the ILPto
read. From the status bits read, the ILPdetermines which
circuit caused the interrupt and branches to the called for
interrupt service routine.If more than one interrupt is
pending, the System f.LPIRQ interrupt handling routine
decides which one needs to be (or can be) handled first.
The order in which it handles these interrupts dependson
the current activity of the System f.LP.
Theory of Operation-2430 Service
The lowest priority is given to the combined signal
forming the IRQ (interrupt request). This interrupt allows
various sub-systems to get attention from the System ILP.
NOR-gate U850B outputs a LO when any of the five con-
ditions occur. Inputs to NOR-gate U850B are from: the
GPIB (General Purpose Interface Bus), the Display cir-
cuitry, the Front Panel, the Waveform ILP, and the Trigger
System. Of these, the latter three interrupts may be
masked off (disabled) by the ILP by writing LO mask bits
into register U760 which are then applied to AND-gates
U880A, U880B, and U880C. A LO input to one input of an
AND-gate holds the associated output pin LO and
prevents an interrupt signal from being gated through to
NOR-gate U850B. The Waveform ILP may mask the
Display System interrupt (DISDN) from the System f.LPby
placing a LO on pin 5 (MDISDN) of AND-gate U580B from
register U550 (diagram 2). The Waveformf.LPthereby can
gain first access to the Display System if it needs to do
display updates before the System ILP sees that the
Display System is finished with its last task. When the
Waveform f.LPis done, it writes the MDISDN interrupt HI to
let the System ILP know that it is finished with the Display
System and the Display System is ready to be restarted.
The next interrupt in priority after the NMI is the FIRQ
(fast-interrupt request). It is produced by flip-flop U894A in
response to a 2 ms clock signal from the Time Base circuit
(diagram 8). The 2 ms clock sets the FIRQ line LO every
2 ms to signal ILP U640 that it is time to do the time-
critical tasks like updating the DAC System. When the
fast-interrupt request has been serviced, the ILP clears the
FIRQ latched into U894A by outputting address 6012h.
This address is decoded by 1-of-8 Decoder U884 to gen-
erate a CLRFIRQ (clear fast-interrupt request) signal that
resets flip-flop U894A. Servicing of a fast-interrupt request
differs from other interrupt requests in that the contents of
only two f.LP registers are pushed to an internal stack
(instead of all theILP registers), allowing the ILP to respond
faster.
over the other two interrupt levels. If either of the other
interrupts is present at the same time as the NMI, the ILP
gives preference to the NMI and immediately branches to
the power-down routine. The power-down routine per-
forms the operations necessary for an orderly shut-down
of the scope. A cyclical-redundancy checksum of the data
stored in Nonvolatile RAM is calculated and stored back
into that RAM. On power-up, that checksum is used to
verify the validity of the parameters and settings stored in
the Nonvolatile RAM. To prevent a possible 50-ohm over-
load of the Channel 1 or Channel 2 input circuitry during
times that the instrument is off, part of the power-down
routine is to make certain that input coupling is set to a
high-impedance state.
To Next Page
Loading...
