Front Panel J.LPU700 is externally clocked by the
4 MHz system clock applied to the external clock input
(EXTAL). Initially, the LO state of FPRESET on the INT2
input (pin 18) will clear all the internal registers of the Front
Panel
J.LP.
When FPRESET goes HI, the J.LPexecutes the
power-up self-test instructions stored in ROM space within
the J.LPintegrated circuit. When the self test has com-
pleted, the Front Panel J.LPsends the diagnostic result byte
to the System J.LPand branches to its main program. The
Front Panel /lP
Front Panel J.LPU700 does the reading of the front-
panel pots and switches. It continuously scans the front-
panel control settings and compares them against the
values stored in its internal RAM. When a change is
detected, the Front Panel J.LPissues an interrupt to the
System
J.LP .
The System J.LPthen handles the interrupt and
reads the changed data from the Front Panel J.LPto update
its control-setting values. The Front Panel J.LPalso updates
the current value list stored in its RAM for further use.
The Front Panel Processor (diagram 3) monitors the
settings of the pots and switches of the Front Panel
(diagram 4) and the Auxiliary Front Panel (diagram 6). The
Front Panel J.LPallows quick system response to changes
in front-panel settings without excessive use of time by the
System
J.LP .
The Front Panel Processor system consists of
the microprocessor integrated circuit with a built-in RAM,
ROM, and
AID
converter (for digitizing the potentiometer
wiper voltages); the handshake logic between the System
J.LPand the Front Panel J.LP(to synchronize data transfer
between processors); and the data bus interface to pro-
vide the actual data transfers between busses.
FRONT PANEL PROCESSOR
To write data into the latch, the controlling J.LP
addresses location 6019h, causing the COMREG line from
U540 to enable U550. Data from the WD bus is written
into the latch on the rising edge of the WWR pulse. The Q
output from pin 2 (MDISDN) of the latch is applied to
AND-gate U580B (diagram 1) where it either masks the
DISDN (display done) interrupt from the System J.LPwhen
it occurs or lets the interrupt pass. Masking the DISDN
interrupt from the System J.LPpermits the Waveform J.LPto
have first access to the Display System for display
updates before the System J.LPsees that the Display Sys-
tem is finished with its last task. The next bit is unused.
The Q output bit on pin 10 is the WPDN (waveform proc-
essor done) interrupt and provides the Waveform J.LPwith
a way of telling the System J.LPthat it is done with its
assigned task and is ready to accept another. The output
bit on pin 10 is applied to Display Status Register U542A
and is used for write-readback verification of U550 and
U542A during the self-check and other diagnostic routines.
3-26
Interrupt Latch
The Interrupt Latch (U550) allows the Waveform J.LP
operations to interrupt the System J.LPfor servicing and,
when servicing is completed, allows the System J.LPto
reset the interrupt.
Display Status Register
Display Status Register U542A allows the controlling
processor (System J.LPor Waveform
J.LP)
to read the status
of the Display System operations. The address-decoded
SSREG (sub-system status register) line from Decoder
U540 enables buffer U542A to place the DISDN (display
done) and ACQDN (acquisition done) signals on the WD
bus where they may be read. These status bits are used
by the reading J.LPto determine when to execute the next
phase of a display or acquisition sequence.
When the oscilloscope is turned off, the secondary sup-
ply voltages drop off slowly enough to allow an orderly
shutdown of the digital circuitry. The RESET signal from
the Power-Up circuit (diagram 1) goes LO when the output
of +5 V
D
supply drops to about +4.3 volts. The LO
"RESET
signal switches off Q332 to produce a high-
impedance path from its collector to ground, and CR784
becomes forward biased by the voltage level of the charge
on C896. The PWR bias supply to Q782 is removed when
the +5 VD supply drops below about +3 V (Q806 in the
Backup Battery Circuit becomes biased off at that voltage
level), and that transistor is also turned off. The positive
voltage level on the RAM chip-select input keeps the out-
puts in their the high-impedance state, and the current
needed to maintain RAM contents is then supplied from
the charge on C896 through forward-biased diode CR784.
During normal operation, the PWR (power) signal from
Q806 in the Backup Battery circuit (diagram 1) will be LO
and the Vee source for Save RAM is via transistor Q782.
With the power on, capacitor C896 is charged up through
CR792 to store energy for the power-off keep-alive func-
tion. Chip selection for the Save RAM is done through
transistors Q244, Q332, and their associated components.
Initially, when the oscilloscope is turned on, the RESET
signal applied to the base of Q332 via CR244 keeps the
Save RAM deselected. When the power supplies are up to
normal operating levels, RESET goes HI, and chip selec-
tion is controlled by the output signal from AND-gate
U580C.
U350 for three to five days at room temperature with a
10 J.LAstandby current demand. The save time decreases
with increasing temperature as the standby current
demand increases and the charge storage capability of the
capacitor decreases.
Theory of Operation-2430 Service
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