A row is selected for checking by the Front Panel jlP
(U700, diagram3) when it switches the MUXSEL lines
(0-2) applied to multiplexer U903 to set a row line LO. To
check the columns, the processor pulses its S/[
(shift/load) select line to shift register U904 first LO and
then HI. This causes a parallel load of the six column-line
bits (pius the seventh and eighth bits tied HI by R934)into
the shift register. The processorthen generateseight shift
clocks (SHCLK)to U904, serially shifting the switch data
out on the SWOUT (switch data out) line. The serial data
bits are applied to the PBO input (pin 25) of the Front
Panel jlP to be checked. Any LO bits in the column-line
data tell the jlP that a switch is closed. Since the Front
PaneljlP knows which row line it set LO, it can determine
from the position of the LO bits in the serial data string
which of the switches are closed.
The Front Panel switches are arranged in an electrical
array of eight rows and six columns.Switches are placed
at row-columnintersections,and when a switch is closed,
one of the row lines is connected to one of the column
linesthrough an isolationdiode.Checkingfor switch condi-
tions (open or closed)is done by setting a single row line
LO and then sequentially checking the six columns to
determine if a LO is present on any of the column lines.
After each column line in a row is checked, the current
row line is reset HI and the next row line is set LO to
check the next six columns. A complete check of the
front-panel switches consists of setting all eight row lines
LO in order and performing a six-column scan for each
columnto check for a LO.
Front-Panel Switch Scanner
The variablesdefiningthe current settings of the control
pots and the front-panel switches are stored and continu-
ally updated in NonvolatileRAM U664 (diagram1) by the
System jlP. The data remains stored when the oscillo-
scope is turned off so that when the scope is turned on
again the System jlP returns to the same front-panel
setup that was presentwhen the scopewas turned off.
All of the Front Panel controls (diagram4) are "soft"
controls in that they are not connected directly into the
signal path. Therefore, associated circuits are not
influenced by the physical parameters (such as capaci-
tance, resistance,and inductance)of the controls. In addi-
tion, convertingthe analogoutput levels of the potentiom-
eters to digital equivalentvaluesallowsthe System jlP and
the Front Panel jlP to handle the data in ways that
enhancecontrol operation.
The Front Panel is the operator's interface for control-
ling the user-selectableoscilloscopefunctions.
FRONT PANEL CONTROLS
3-28
The Front PanelTrigger Status Indicatorsprovidevisual
information regarding trigger slope and trigger status to
the user. Data written to LED RegisterU741from the Sys-
tem jlP turns on the LED that reflects the current trigger
status. A LO output from U741 turns on the associated
LED. The LED Register is enabledby a System jlP write
to address6208h.Trigger Holdoff DecoderU781 (diagram
12) produces the decoded LEDREG signal that enables
data at the input pins to be latched when the WR clock
goes HI.
Trigger Status Indicators
When U700 servicesthe interrupt by the System ,uP,it
sets FPRD (front-panel reading) LO and enables the
latched data in register U742 onto the Front Panel data
bus. It then reads the data into its internal registers and
asserts FPDNRD (front-panel done reading). FPDNRD
going HI clocks the FPDNRD status bit from flip-flop
U861A pin 6 HI to signal the System jlP that it is done
reading the byte and removes the WRTOFP interrupt
present on U861A pin 5. Each data byte transfer from the
System jlP to the Front PaneljlP and vice versa is done
usingthe two handshakeroutinesjust described.
When the System ,uPneedsto write to the Front Panel
,uP,it writes data to address6209h.This latchesdata from
the System ,uPdata bus into register U742.The enableto
U742 is via U862C. The latch enable also resets the
Q
output of flip-flop U861A LO via U862D to produce the
WRTOFP(write to front-panel)interrupt to U700. Latching
data into U742 immediately frees the System ,uP to
resume other tasks, since it doesn't have to wait for the
Front PaneljlP to servicethe interrupt.
Dependingon what the System ,uP is doing, it may
either service the interrupt request immediately,or it may
wait for time to be available.Whenit respondsto the inter-
rupt, it does a read of the Front Panel"register" at
address 6209h. The decoded FPREGsignal from Trigger
Holdoff Decoder U781 (diagram 12) allows OR-gates
U862B and U862Cto pass the WR or RD signals. For a
read, both input pins to U862B are LO,causingthe output
of U862Ato go LO. This enablesbuffer U751,placingthe
data from the Front Panel,uPon the System ,uPdata bus
(FPO-FP7)and, at the same time, resets flip-flop U861B.
Resetting U861B removes the front-panel interrupt and
sets HOSTDNRD(host done reading)to U700HI.
bytes to be given to the System ,uPon its PA
o
-PA
7
(port
A-bits 0 through 7) outputs. It then asserts WRTOHOST
(write to host) HI, clockingthe FPINT(front-panelinterrupt)
at the
Q
output of U861B HI.
Theory of Operation-2430 Service
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