3-29
The magnitude (range) of the DAC output currents is
set by the voltaqes applied to pins 14 and 15 of U860.
Pin 15 V
REF-
is tied to ground through R761. The refer-
ence voltage to pin 14 is applied via a voltage divider
(R760 and R860) between the
+
10 V
REF
supply and the
output of the DAC Gain Sample-and-Hold,U660. The Sys-
tem ILPenablesself-calibrationof the gain of U860via this
Sample-and-Holdcircuit. Gain changes are explained in
the discussionof the DAC Gain Self-Calibrationcircuit.
Only the first 12 bits (DACOthrough DAC11)of the 16
bits loaded into the registers for are used for conversion
data. The next three higher bits are used as 1-of-8 select
bits to the four analog multiplexers that route the DAC
output voltage to the proper Sample-and-Holdcircuit. And
finally, the MSB of shift register U851 is used in a write-
readback operation that allows the operation of registers
U850 and U851 to be checked by the System ILPduring
self checks and diagnostics.
The
D/A
Converter stage, U860, converts the digital
value written into registers U850 and U851 by the System
ILPinto two complementaryoutput currents. (Complemen-
tary in this case means that the sum of the two currents
equals a predefinedvalue.)The digital data bits to be con-
verted are serially clocked into the shift register from data
bus line D7 (via U280). Sixteen data bits are sequentially
placedon data bus line D7 and clocked into the shift regis-
ter on the rising edges of 16 WR pulses (clock is via
U280A and U280B).As the bits are being loaded into the
registers, the DAC output current does not correspond to
any useful value, but the multiplexers used to direct that
output to the following stages are not enabledduringload-
ing. After all 16 bits have been clocked into the register,
the inputs to DAC U860 will be at their proper levels and
the DAC outputs will be valid levels. One of the multi-
plexers may then be enabled by the System ILPusing the
DAC MUX enablesvia register U272.
D/A
Converter
The other portion of diagram 5 is the Acquisition Con-
trol Registers circuitry, used by the System ILPto set up
the acquisition and triggering modes. The System DAC
portion is describedfirst.
The System DAC portion of the circuitry consists of a
data latch that stores the digital value to be converted, a
D/A
converter that does the actual conversion, a multi-
plexer system to route the resulting analog voltage to the
proper control circuit, and a sample-and-holdsystem that
stores the analog levels between updates. Much of the
multiplexing and sample-and-hold circuitry is shown in
diagram 6, System DAC(cont) and Auxiliary Front Panel.
Theory of Operation-2430 Service
The System DAC and Acquisition Control Registerscir-
cuitry (diagram5) is used to set various analog reference
voltages throughout the instrument and controls such
things as preamplifiergain, vertical position and centering,
trigger levels, holdoff time, common-moderejection, grati-
cule illumination,and CCD offsets.
SYSTEM DAC AND ACQUISITION
CONTROL REGISTERS
Three MUXSEL control lines to multiplexers U902 and
U600 select the pot or value to be read. The analog volt-
age level at the wiper of the pot selectedby U902 is out-
put at pin 3 (AOUTO)and is applied to the Front PanelILP
at pin 21 (analog input ANO).Analog voltages selected by
multiplexer U600 are applied to analog input AN2. The
voltage levelsat these inputs are digitized,and the amount
and direction of changesfrom the previouslystored values
are calculated. Changed values are stored in the internal
RAM of U700 for comparisonduring future scans, and the
change data is then relayed to the System ILP. That
change data is used by the System ILP to update its
current control settings and pot values list and to update
the front-panelvariablesin NonvolatileRAM U664.
Pot Scanning
The Pot Scanning circuitry, working together with the
AID
converter internal to Front PanelILPU700, produces
digital values for the wiper voltages of the front-panel
potentiometersand for the voltages monitored by the aux-
iliary front-panel circuitry. Analog multiplexer U902 selects
which of the eight front-panel pots are read. (Trigger Level
control R902 and Holdoff control R901 are continuous-
rotation potentiometers made up of two separate resistive
elements each.) Analog multiplexer U600 (diagram6)
selects the auxiliaryfront-panel valueto be read.
In addition to the front-panel push-button and
continuous-rotation switches connected in the switch
array, there is a rate switch associated with the Horizontal
Position, the CH 1 Vertical Position, the CH 2 Vertical
Position, and the Cursor Position potentiometers. These
switches are normally closed in the center positioning
range of the associated pot. When the pot is rotated in
either direction out of this range, the rate switch opens.
The open switch signals the Front Panel ILPthat the asso-
ciated control function has changed from normal(absolute)
positioning to a faster, rate-change positioning mode.
Rotating the pot still further into the rate region causes the
associated on-screen display position to change at a still
faster rate. When the pot position is returned to its center
range (rate switch closed), further positioning of the asso-
ciated display occurs from where the rate function posi-
tioning left off.
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