Sample-and-Hold
The eight Sample-and-Hold circuits shown on diagram 5
(formed by U641A through U641D, U650, U660, U661A,
U661B and their associated components) store and buffer
the analog voltage levels directed to them by multiplexer
U651. Each of the operational-amplifier circuits selectable
by U651 (except the DAC Offset and DAC Gain opera-
tional amplifiers, U650 and U660 respectively) has a hold
capacitor on one input that is charged up to the DAC out-
put voltage level through the selected multiplexer channel.
When the multiplexer channel is then deselected, the capa-
citor holds the voltage at a fixed level so that the associ-
ated Sample-and-Hold circuit provides a steady voltage
level to the circuit it controls. Voltage gain of the Sample-
and-Hold operational amplifiers range from more than 4.5
in the CH 1 and CH 2 Gain-Cal circuits down to 2 in the
Multiplexer U551, when enabled by Multiplexer Select
Latch U272, routes the analog output voltage from DAC
I-to-E Converter U661C to one of eight Sample-and-Hold
circuits, depending on the output specified by the logic
states on the its select inputs. Selection is determined by
three bits clocked into DAC Register U851 as described in
the preceding D/A Converter discussion. One of three
other multiplexers, shown in diagram 6, may be enabled
instead of U651 to pass the DAC output to one of the
Sample-and-Hold circuits on their outputs (also shown in
diagram 6).
Multiplexer Select
The Multiplexer Select circuit, composed of addressable
latch U272 and the associated decoding gates, provides
the enabling signal that selects one of the four 1-of-8 mul-
tiplexers to route the DAC output voltage to the Sample-
and-Hold circuits. Data applied to the 0 input of U272
from data bus bit 07 (via U280D) is latched to the
addressed output pin as determined by the logic levels on
the A, B, and C select lines (AO through A2). The input
data is written to the addressed output on the falling edge
of the enable signal at pin 14 (via U280A and U280C). The
logic state written to the output remains latched when the
enable signal returns HI. The states of the unaddressed
outputs remain unchanged. To enable the latch, NOR-gate
U280A (functioning as a negative-logic NAND-gate) needs
the DACSEL (DAC select) line LO to produce a HI output.
That HI is inverted by U280C to enable the Multiplexer
Select register to be written into. That same LO DACSEL
is applied to NOR-gate U280D to enable it to pass the
data on the 07 line to the 0 input of U272 and to the DAC
input register, formed by U850 and U851.
deviation from the correct +1.25 V level produces a gain-
correction voltage applied to the DAC via R760. Capacitor
C662 maintains the correction voltage between DAC
update cycles.
3-30
To set the DAC Gain, the System j.tPloads OF59h into
DAC input registers U850 and U851 and routes the result-
ing output voltage to DAC Gain Sample-and-Hold U660 via
multiplexer U651 pin 2. A digital input of OF59h to the
DAC is supposed to produce an output of +1.25 V from
U661C. The resulting DAC output is compared to a
+1.25 volt reference by operational amplifier U660. Any
CAC GAIN. The DAC Gain is set during each DAC-
update cycle immediately after DAC Offset is set and
keeps DAC gain constant with time and temperature
changes.
Capacitor C655 holds the offset level constant between
update cycles (every 64 ms) to keep the proper offset for
the entire DAC cycle. By updating the offset every 64 mil-
liseconds, offset variations that would otherwise occur
over time and temperature changes are eliminated.
At the beginning of each DAC-update cycle, the System
j.tP writes 0800h to DAC input shift registers U850 and
U851; this corresponds to zero volts (center of the DAC
range). The DAC output currents representing zero volts
are converted by the DAC l-to-E Converter U661C to a
voltage that is applied to U650 via multiplexer U651. Any
deviation from the desired zero-volt level causes the out-
put of U650 (configured as an inverting integrator) to shift
slightly. This applies an offsetting voltage to DAC l-to-E
Converter U661C via R666 and R665 to bring its output
level back to precisely zero volts.
CAC OFFSET. The DAC Offset level is self-adjusting
and is updated via DAC Offset Sample-and-Hold U650
each time the DAC System cycles through its DAC chan-
nels to update its control levels.
The output currents from DAC U860 develop a voltage
drop across the resistive networks at the inputs to opera-
tional amplifier U661C. The equivalent input impedance at
both inputs is approximately 200 ohms; so, when both
currents are equal (middle range of the DAC), the output
voltage of operational amplifier U661C will be close to zero
volts. An offset current is added to the non-inverting input
node via R666 to precisely set the midrange value to zero
volts. The gain of U661C is set by the ratio of R663 to
R664, and the (calibrated) output voltage ranges from
-1.36 V to +1.36 V.
CAC 1-TO-E CONVERTER. This circuit changes the
differential output currents from DAC U860 into a single-
ended output voltage that is routed to a selected Sample-
and-Hold circuit via one of the analog multiplexers.
Theory of Operation-2430 Service
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