3-31
Z-Axis Control
The Z-Axis Control stage consists of
0810.
U811.
U810A. U810B. five-transistor array U812. and associated
components. Multiplexer U811 selects one of three
intensity-control voltages-normal. intensified. or readout
(output from Sample-and-Holdbuffers U820B. U820C. or
U820D) and routes it to a current source composed of
U810A. U810B. and
0810.
The amount of current passed
by
0810
controls the display intensity. The transistors in
array U812 form an automatic gain compensation circuit
for Z-Axis AmplifierU227 (diagram19).
Cal Signal Amplifier
The Cal Signal Amplifier (U610) operates in a manner
similar to the Sample-and-Holdcircuits just described.It is
used to supply test signals to the CAL inputs of the CH 1
and CH 2 Peak Detectors (U440 and U340. diagram 10)
for Self Calibrationof the acquisitionsystem. The test sig-
nal level. stored on capacitor C733. is applied to the input
of an amplifier internal to U610 which has dual-differential
outputs. The complementary-current outputs for each
channelare approximately6 mA
±
1.25 rnA.
A separate Sample-and-Holdcircuit is associated with
each of the multiplexer outputs. An analog voltage routed
from the DAC l-to-E Converter through the selectedmulti-
plexer channel charges up the hold capacitor at the input
of an operationalamplifierin the selectedSample-and-Hold
circuit. When that multiplexer channel is deselected. the
voltage level is held on the capacitor becauseof the high-
impedance discharge paths presented by the multiplexer
output and the operational amplifier input. The individual
operational amplifiers are configured as buffers with volt-
age gains varying from -0.47 to +10. dependingon the
requirementsof the function that is being controlled. The
CH 1 and CH 2 Position Sample-and-Hold circuits also
provide a dc offset of their output levels to properly bias
the inputs they drive.
Sample-and-Hold
DAC Multiplexers
DAC Multiplexers U821. U830. and U831 route the
analog output voltage from DAC l-to-E Converter U661C
(diagram5) to the various Sample-and-Hold circuits.
Operation of each multiplexer is identical to that of Multi-
plexer U651. previously described in the System DAC cir-
cuit discussion. Each multiplexer is individuallyenabled by
a bit from Multiplexer Select Latch U272. and signal rout-
ing through the enabled device is controlled by the three
select bits applied to it from the three most significant bit
outputs of DAC Register U851.
Theory
of
Operation-2430 Service
The DAC multiplexing and sample-and-hold circuits
included in diagram6 operate similarly to those described
in the DAC System (diagram5) discussion. The analog
voltage output from the DAC I-to-E Converter is routed
through one of the three additional multiplexers(shown in
diagram6) to severaltypes of hold circuits.
SYSTEM DAC (cont) AND
AUXILIARY FRONT PANEL
The ACD lineis shared by all the Acquisition Control
Registers;the selectedclock determineswhich register will
be loaded with the data being written by the SystemJ.LP.
DecoderU271 is enabledwhen the ACOSELand WR lines
are La and address line A3 is HI. Address lines AO.A1.
A2 determinewhich of the output lines producesthe clock
signal. A data bit present on the ACD line (previouslywrit-
ten to latch U272 in a DAC write cycle) is loaded intothe
clocked register on the rising edge of the WR signal as
U271 becomesunenabledand its selectedLa output goes
HI. Each bit to be loaded must be successivelywritten to
U272 then moved into a register by the output clock
from U271.
Acquisition Control Registers
Mode control of the analog acquisition system and
trigger circuitry is controlled by the System J.LPvia shift
registers and a decoder. The System J.Lp.through its
address decoding circuitry. enables Decoder U271 to pro-
duce a shift register clock at one of its eight outputs.
These clock signals are used to move serial data from the
ACD (acquisitioncontrol data) line. U272 pin 5. into one of
the various Acquisition Control Registers. of which three
are shown in diagram 5. They are Peak Detector Control
Register U530. Gate Array Control Register U270. and
Trigger Source Control Register U140. Other registers
clocked are the Channel1 and Channel2 Control Regis-
ters (U510 and U220 on diagram9). the internal control
registers of the CH 1 and CH 2 Preamplifiers(U420 and
U320 on diagram9). and the internal control registers in
the AlB Trigger Generator(U150.diagram 11).
Jit 1 Gain and Jit 2 Gain amplifiers and down to about 1
for the CH 1 and CH 2-BAL voltage followers. The Jitter
Gain circuits (formed by U661A and U661B) produce a
negative 5 V dc offset voltage at their output pins as their
gain-setting resistors are referenced to the+5 V supply.
The DAC Offset and DAC Gain Sample-and-Hold circuit
operations are described in the previous
01
A Converter
discussion.
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