3-33
To obtain minimum delay, U622, US23B, and their
associated logic gating are configured as a divide-by-20
counter whose output is synchronizedto the 20 MHz clock
(plus propagation delay through US23B). Counter U622
and NAND-gate U620C provide division by ten, producing
a 2 MHz clock (4XPC) at pin 11 of U622. This clock is
inverted by US13Fand is used in the A/D Converter and
Acquisition Latches circuit (diagramlS). The uninverted
4XPC clock is used as the SR (shift right) data input for
shift register U642 to produce two delayed 4XPC clocks
(D
1
4XPC and D24XPC).
Minimum-Delay 1 MHz Clock
The Minimum-Delay 1 MHz Clock circuit produces a
1 MHz clock (2XPC)whose transitions very nearly coincide
with those of the 20 MHz clock. The requirementsof the
clock timing dictate that the delay betweena rising edgeof
the 20 MHz clock (C20M2on U720A pin 3) and the 2 MHz
TTL4C (TTL-compatible phase4 clock, originating from
Phase Clock Array U470-diagram 11) transitions be less
than 50 ns. Since the propagation delay (2XPC-to-TTL4C
delay) through the Phase-ClockArray is a significant por-
tion of the SOns allowed, the phase of the 2XPC (two-
times CCD "C" register clock rate) clock relative to the
20 MHz clock must be optimizedfor minimumdelay.
The CLK1A, CLK2A, and CLK3A clocks are bufferedby
U712A,U712C,and U712Dto the WaveformJ.LP.Buffering
these clocks ensures that a fault on the buffered side will
not halt operation of the Secondary Clock Generator cir-
cuit. Series-damping resistors R713, R715, and R716
reduce ringing in the interconnection cable. The 5 MHz
clock is appliedto multiplexer U722A, where it is available
for selection (along with the 4MHz clock) as the reference
signal to Phase Clock Array phase-locked loop circuit
(U381, diagram 11). The 5 MHz clock is also used in the
DisplayControl circuitry, diagram 17.
Flip-flopU710D and exclusive-ORgate U711C generate
the 2.5 MHz clock (CLK3A) that is delayed 3/8 of a cycle
(150 ns) with respect to the 2.5 MHz clock at the 3Q out-
put (CLK1A). CLK1A, CLK2A, and CLK3A are used for
control-clock generation in the Waveform Processor sys-
tem (diagram2). The 10 MHz clock output at J133 is pro-
vided as a trigger signal when troubleshooting the
Waveform Processor system with a logic analyzer or test
oscilloscope.
Secondary Clocks
The Secondary Clocks circuit further divides the
20 MHz clock to produce other system clock rates. The
flip-flops within U710, along with logic gates U711A,
U711B, U711C, and U712B, produce 10 MHz, 5 MHz, and
2.5 MHz clocks.
Theory of Operation-2430 Service
Jumper J132 allows an external clock signal to be sub-
stituted for the 40 MHz clock signal to aid in testing and
troubleshooting.
The divide-by-fivecircuit is a state machineformed by
J-K flip-flops U612B, U615A, and U615B. With the two
feedback signals to the J and K inputs of U612B, the flip-
flop chain sets logic level on the J and K inputs of U615B
that allows its Q output to change states only every five
40 MHz input clocks to producethe 8 MHz clock.
The Master Clock circuit produces 20 MHz and 8 MHz
clocks (C20M and C8M) by dividing down the output from
the 40 MHz crystal oscillator circuit, Y611. The oscillator
circuit drives both the divide-by-two flip-flop (U612A) and
the divide-by-five circuit (flip-flops U612B, U615A, and
U615B)in parallelvia inverter U513A.The 20 MHz clockis
obtained from flip-flop U612A.With its Set, Clear,J, and K
inputs all held permanentlyHI, the flip-flop toggles on each
negative-going40 MHz clock edge to dividethe input clock
frequencyby two.
Master Clock
The System Clocks circuitry (diagram 7) produces the
fixed-frequencySystemclocks signals usedthroughout the
oscilloscope.These clocks are developedfrom a 40 MHz
master clock frequency, and they are used to drive state
machines that produce other special-purposeclocks that
control the waveform acquisitionprocesses.
SYSTEM CLOCKS
Auxiliary Switch Register U700 performs a parallel load
of the status of all of itsinput bits whenever the Front
Panel J.LPputs out a SHCLK (shift clock) with the
siC
(shift/load) select input of the register set LO. Once
loaded, the S/[ input is set HI, and the eight bits of
switch-closuredata are clocked out to the Front PanelJ.LP
on the SWOUTA (switch data out-auxiliary Front Panel)
linewith eight moreclocks appliedto the clock input of the
Auxiliary Switch Register. Switches read include the five
menu select switches on the lower edge of the crt bezel,
the Intensity Control SELECTswitch, the STATUS switch,
and the MENUOFF/EXTENDEDMENU switch.
OVL levels (used to indicate when an excessive voltage is
applied to the input connector), or one of the two, 180
degree out-of-phase wipers on the Intensity control (a
continuous-rotation pot).
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