After 0100 is loaded into counter U621, the LOAD out-
put of U623B returns HI (since pin 12 of U621 has been
set HI by the inputs loaded into the counter). This once
again produces a LO LOAD output from inverter U513E
and prevents U730 and U830 from shifting. Counter U621
counts four cycles of the 20 MHz clock (200 ns), reaching
count 0111.The next 20 MHz clock toggles the
Q
c output
of U621 La and sets the LOAD line La once again, ena-
bling shift registers U730 and U830. The next clock
(250 ns) shifts the previouslyloaded La from the OS1 out-
put right to the OS2 output of U730 and moves a HI from
the SR data input into the OS1 output. At the same time,
counter U621 is reloaded to 0100 binary to again restart
its count.
When the SYNC4Coutput of flip-flop U720A returns HI,
counter U621 is enabledby the HI from AND-gate U623B
to count for three, 20 MHz clock cycles (150ns), reaching
the count of 0111 binary. The next clock toggles the
Q
c
output of U621 La (count goes to 1000 binary), and the
LOAD output from AND-gate U623B is forced La. The HI
LOAD signal output obtained from inverter U513E, along
with the La SYNC4Cfrom flip-flop U720A pin 6, sets up
shift registers U730 and U830 to shift right. The next
20 MHz clock (250 ns after the 2XPC clock toggled) shifts
a La to the OS1 output of U730 (pin 14) and loads a
binary 0100 into counter U621 (sincethe output of NAND-
gate U620B is now La). The fixed HI applied to the SR
data input of U730 is shifted to the
Q
A
output.
When the SYNC4C(synchronizedphase-4 clock) is La
(pin 5 of flip-flop U720A),the LOAD signal applied to shift
registers U730 and U830 (via AND-gate U623B and
inverter U513E) will be HI. This HI, along with the HI
SYNC4Csignal from pin 6 of flip-flop U720A, causes both
shift registers to do a parallel load of the fixed logic levels
applied to their 0 input pins. The levels loaded set the
OS1 (sampleCH1-CCD outputs), OS2 (sample CH2-CCD
outputs), and the RST (reset CCD output wells) outputs
from U730, and the SYNC (sync data clocks) output from
U830 all HI. The HI RST level applied back to U621 and
the HI output from NAND-gate U620B will be loaded into
counter U621 as 0101 binary because of the La LOAD
output of U623B appliedto the
CT/LD
input pin. This state
then stays as is for the remainderof the La state of the
SYNC4Csignal.
When acquired samples are to be shifted out of the
CH1 and CH2 CCD array, the TTL version of the Phase-
Clock 04 output (TTL4C from Phase Clock Array U470)
will be toggling at 500 kHz. Transitions of the TTL4C clock
are resynchronizedto the 20 MHz clock (C20M2) by flip-
flop U720A to correct the phase betweenthe TTL4C clock
and the state machine outputs. This correction closely
synchronizescharge transfers within the CCD (relative to
the 2XPCclock)with the signaltransfers out of the CCD.
3-34
CCOOutput-Sample Clocks
The CCD (charge-couple devices) Output-Sample
Clocks stage controls signal transfers from the Acquisition
CCD-ClockDrivers (diagram10) to the external CCD Out-
put circuitry (diagram14). It consists of a state machine
synchronized to the 20 MHz clock (and thus the CCD
events) and produces Clocks to: (1) move sampled data
out of the CH1 CCD array, (2) move sampleddata out of
the CH2 CCD array, (3) reset both the CH1 and CH2 CCD
array output-charge wells in preparation for the next
transfer, and (4)phase-lock the CCD-Data Clock stage.
Figure 3-3 illustrates the timing of these clocks and other
clocks in the System Clock Generator; it may be of use in
followingthe discussionof circuit operation.
The
Q
output of U523B will stay HI until the next seven
(0111)state from AND-gate U623C arrives, at which time
the
J
and K inputs are again set HI. On the rising edge of
the next 20 MHz clock the
Q
output of flip-flop U523Btog-
gles La. When the 50 ns pulse from U623C returns La,
the
J
and K input states will both be La, and further
20 MHz clocks are prevented from changingthe
Q
output
state of the flip-flop. The output remains La until the next
HI state from U623C starts the divide sequence over
again. Note that transitions of the 1 MHz signal (2XPC)at
pin 9 of U523B are delayedfrom the C20M (20 MHz clock)
clock rising-edgetransitions by only the propagationdelay
through the flip-flop(about 7 ns).
AND-gate U623C watches the three lowest bits of the
counter outputs (Q
A,
Qs, and Qc). The output of U623C
(pin 8) will be HI during the
"7"
state (0111 binary)of each
10-countcycle and will stay HI for one 20 MHz clock cycle
(50 ns). This HI is applied to the K input and the
J
input
(via OR-gate U522B)of flip-flop U523B. With the K and
J
inputs both HI, the flip-flop toggles when the next 20 MHz
clock arrives. Assuming the
Q
output of the flip-flop was
La, togglingto a HI applies a HI to the
J
input via OR-gate
U522B. When the output of U623C returns La (next
20 MHz clock), the
J
and K input states of the flip-flop will
keep the
Q
output HI with subsequent20 MHz clocks.
After one run through the counting cycle at power-on,
any unknown counter states in divide-by-ten counter U622
are resolved, and the circuit counts in the following
manner: If the circuit does not start in the Load condition,
it will be in the Count mode (a HI on pin 9 from the output
of NAND-gate U620C) and the 20 MHz clocks cause the
counter output to increment until it reaches 1100 (binary).
At this point the output of U620C will go La, causing the
counter to load the count 0011 (binary) from its inputs with
the next clock. Once the counter is loaded, the output of
U620C will return HI, and normal counting from a known
state commences. When the counter reaches 1100 again,
the load-count sequence will be repeated, requiring ten
20 MHz clocks to complete the cycle.
Theory of Operation-2430 Service
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