The delayed D14XPC and D24XPC clocks are produced
by using the 4XPC clock as the data source for the shift-
right input to register U162 and clocking that data right to
the shift register outputs with the 20 MHz clock (C20M1).
The first output signal (Q
A)
is delayed from the input clock
by 50 ns and the second (Qc) by 150 ns. D
2
4XPC is
applied to NAND-gate U650B (diagram 8) for use is con-
trolling the timing of the SAVEACQ signal to the Acquisi-
tion Memory. The time delay ensures that the data written
to Memory has stabilized at the output of the
AID Converter.
The DS21 signal is also applied to a circuit formed by
flip-flop U720B and exclusive-OR gate U711D. One input
of U711D is held permanently HI so the gate acts as an
inverter for the DS21 signal on the other input. When the
DS21 logic level goes HI, the output of U711D goes LO
and flip-flop U720B become set with the Q output (pin 9)
HI. At the end of the HI logic level, the DS21 signal goes
LO, but the Q output remains HI until the next rising edge
of the D
j
4XPC clock (4XPC delayed by one 20 MHz clock
cycle) clocks the LO on the D input through the flip-flop.
This circuit action has the effect of stretching the DS21
signal by 50 ns. The resulting DDS21 signal is applied to
Time Base Controller U670 (diagram 8).
Similar 500 ns count cycles shift the HI bit to each out-
put of shift register U831 in succession until, during the
last 50 ns of the HI state of the DS13 signal (U831 pin 15),
SYNC goes LO again. The LO sets up U721 and U831 to
load on the next 20 MHz clock. The next clock (concurrent
with TTL4C going LO) loads both U721 and U831 and
starts the cycle over again. The arrival of the SYNC signal
ensures that the presetting load of U721 and U831 always
occurs concurrently with TTL4C going LO. The four data-
select clocks (and their inverted outputs) are thereby syn-
chronized to CCD array output cycles.
That same 20 MHz clock loads counter U721 with 0111
binary and clocks SYNC from pin 15 of U830 HI. With
SYNC HI, shift register U831 is in hold mode, and counter
U721 is enabled to count via AND-gate U623A. Counter
U721 increments from the beginning count of 0111 to
0000 (nine, 20 MHz clocks-450 ns), at which time the
SHIFT output from OR-gate U522A goes LO. This sets up
shift register U831 (via U620A) to shift and via U623A
places U721 in load mode. The next 20 MHz clock (at
500 ns) shifts a new LO from the SR data input of U831
into the Q
A
output and shifts the HI from the Q
A
output to
the Q
B
output (DS11). Counter U721 is also reloaded with
0111 binary for the next count cycle.
3-36
When the SYNC output from U830 pin 15 goes LO (for
50 ns at the end of the TTL4C cycle), the outputs of
NAND-gate U620A and inverter U513D go HI, and the out-
put of AND-gate U623A goes LO. This places counter
U721 and shift register U831 in their parallel load mode,
and the next 20 MHz clock rising edge (start of next
TTL4C) loads in the fixed logiClevels at their D inputs. The
data bits (1000 binary) loaded into shift register U831 set
the DS23 (data select CH2 phase-3) output bit (pin 15) HI,
with all other output bits LO. The LO DS23 output from
inverter U832D is applied to Q880 (diagram 14) to switch
the CCD output data from the CH2 CCD array phase-3
output onto the CCD DATA line, where it is applied to AID
Converter U560 (diagram 15).
CCO Data Clocks
The CCD Data Clocks (DS11, DS13, DS21, and DS23),
generated by counter U721, shift register U831, and the
associated logic gating, are responsible for multiplexing
the four CCD array output levels (CH 1-1, CH 1-3, CH 2-1,
and CH 2-3) onto the CCD DATA line for digitization by
the AID Converter. Figure 3-3 (shown previously) illus-
trates timing of the stage.
AND-gates U731A, U731B, and U731C buffer the out-
puts of counter U730 and ensure that the counter and the
clock circuit will keep running even if a short occurs on the
buffered OSAM1, OSAM2, or RESET lines.
Since U621 now needs one less clock to count to 0111,
RST (and thus RESET remains LO for 200 ns (rather than
250 ns as for OS1 and OS2), after which time the next
load of U621 will occur. At the end of the reset time, both
RST and the DA output of U620B are both LO, so counter
U621 loads to 0000 binary. On the same 20 MHz clock,
the LO RST level present on the SR data input of U830 is
shifted right to the Q
A
(SYNC) output. This state (with
SYNC LO) lasts one clock cycle (50 ns) only, because Qc
is still LO, causing LOAD to go HI and, therefore, causing
the shift register to again shift right, resulting in SYNC
going HI. On the next 20 MHz clock pulse, the TTL4C
input is LO, causing SYNC4C to go LO on the clock edge.
This starts the whole process over, and it is repeated until
all samples have been moved out of the CCD arrays.
A similar 250 ns cycle occurs for the OS2 LO state,
ending with the LO being shifted to the Q
D
output of
U730. However, when the load is done to U621 this time,
the OS2 output to NAND-gate U620B is LO, and counter
U621 is loaded with 0101 binary (the D
A)
input from
U620B is HI).
Theory of Operation-2430 Service
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