3-37
The FISO (fast-in, slow-out, pin 36), ROLL (pin 2),
SEL4/5 (select reference-4 MHz/5 MHz, pin 28), and
ENVL (envelope,pin 39) outputs are set indirectly by Sys-
tem lIP writes to the internal control registers at the start
of each acquisition cycle. Control signals are then output
by an internal state machine of the Time Base Controller
The instruction registers within Time Base Controller
U670 are enabledwhen TBSEL from the SystemlIP is LO.
A register is selected for writing to or reading from by
address lines AO,A1, and A2. Setup data from the System
lIP data bus is bufferedto the selectedregister via bidirec-
tional buffer U641 and written into the selected internal
register by the WR (write) Signalappliedto pin 14. Acquisi-
tion mode, SEC/DIV setting, trigger position, and several
other functions are controlled by the System lIP via the
commandswritten to the instruction registers within U670.
Status data and register contents may be read out of the
Time Base Controller registers by the System lIP in a simi-
lar manner using the RD (read) signal to reverse the data
paths in buffer U641and the internalcircuitry of U670.
• Ensure that the proper number of post-trigger sam-
ples are stored into the Acquisition Memory after the
trigger event.
• Ensurethat enough sampleshave been saved in the
Acquisition Memory to fill pretrigger requirements
beforeenablingthe Triggers.
• Synthesize the proper sample rate called for by the
SEC/DIVsetting.
• Ensure that valid data has made it through the
"short-pipe" path of the CCD arrays.
Major functions in Short-Pipemode are:
• Ensure that exactly 1024 samples are moved to the
Acquisition Memory during the "slow-out" conver-
sion process.
• Discard the proper number of unneededsamples at
the start of"slow-out" conversion.
• Ensure that the proper number of "post-trigger"
samples are moved into the "B" register after
triggering occurs.
• Ensure that enough samples are in the CCD array
"B" register to fill the"pretrigger" requirements.
The major Time Base Controller functions in FISO
(fast-in,slow-out) mode are:
Theory of Operation-2430 Service
Time Base Controller U670 monitors and controls the
various acquisition functions. Two different operating
modes of the CCD (charge-coupleddevices) arrays must
be controlled by U670; these are the FISO mode (fast-in,
slow-out) and the Short-Pipe mode (slow-in, slow-out).
FISO mode is used at sweep speeds faster than
100 IIs/div when the analog sampling must occur at the
fastest possible rate. The Short-Pipe mode is used for
lower frequency signals when the A/D conversion rate is
muchfaster than the signalsbeingsampled.
Time Base Controller
Time Base Controller (U670, diagram8) andits associ-
ated gating circuitry generates the control signals and
clocks to cause acquisitions in the various modes to
occur. It keeps track of how the acquisitionis progressing,
starts the digitization of the samplesby the A/D Converter
when the correct number of data points have been
acquired, and moves the digitized samples to Acquisition
Memory (U600). The Acquisition Memory provides tem-
porary storage of the converted data to permit the
WaveformlIP to accessthe data as it is neededto update
the display.
TIME BASE CONTROLLER
AND ACQUISITION MEMORY
Flip-flop U523A is configured as a divide-by-two circuit
that divides the 8 MHz (C8M) clock to produce a 4MHz
clock at its
Q
output (pin 6). The SEL4/5 (select
4 MHz/5 MHz) signal on pin 14 of U722A selects whether
this 4 MHz clock or the 5 MHz clock from U710 will
appear at the REF4/5output pin. The signal inputs to the
multiplexer are connected so that when SEL4/5 is HI, the
5 MHz clockis selected (no matter what state the other
select input, shown with U722B, is in); when it is LO, the
4 MHz clock is selected. The 4MHz signalis inverted by
U832F and applied to the Front-Panel lIP (U700,
diagram3) as the clockingfrequency.
Reference Frequency Selector
The PLL (phase-locked loop) Reference Frequency
Selector, U722A, selects either a 4 MHz or a 5 MHz clock
signal as the reference frequency to the Phase-Locked
Loop (PLL) circuit (U381, diagram 11). The Phase-Clock
Oscillator in the PLL circuit runs at 50 times the selected
reference frequency, so sampling clocks to Phase Clock
Array U470 are generated at a rate of either 200 MHz or
250 MHz. The two choices of signal frequencies provide
the correct input frequency to the internal dividers of the
PhaseClock Array neededto generatethe clocks for each
SEC/DIVsetting samplerate.
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