When the Waveform JiP (U470, diagram 2) reads the HI
ACQDN status via U542 (diagram 2), it reads the address
of the last-saved point from the Record-End Latch (U502
As the digitized samples are moved to Acquisition
Memory, an internal counter in Time Base Controller U670
watches the DS21 and OS23 clocks (pins 6 and 17) to
determine when 1024 points (or 512 max/min pairs in
Envelope mode) from each CCD array (CH 1 and CH 2)
have been stored. When 2048 samples have been saved,
the Time Base Controller will set ACQUIRE (pin 24) LO,
disabling memory saves, and it will set its ACQDN
(acquisition done) status line (pin 25) HI. The Waveform JiP
(U470, diagram 2) then takes over for transfer of the
acquired waveforms to the Waveform JiP Save Memory.
When the Time Base Controller is in control of writing
data to the Acquisition Memory, the SAVEACQ clock is
routed through U501 of the Mode Control Logic and
becomes the WE (write enable) clock used to write
waveform data into Acquisition Memory U600. That data
is obtained from the Acquisition Latches (diagram 15) via
buffer U613. The WE signal is also used to increment the
Memory Address Counter (U300, U400, and U401) the
result being that digitized samples from the Acquisition
Latches are saved interleaved in consecutive memory loca-
tions. Each address is latched into the Record-Start
Address Latches (U502 and U601) as the data-write ends,
so that the address of the last-stored sample is always
available. This information is used as a pointer when gen-
erating waveform displays.
Once the extra samples have been counted, the
ACQUIRE output is set HI, enabling U650B. Since the
instrument is in FISO mode, the output of U512C will be
HI and the SAVEACQ signal used to save waveform data
into the Acquisition Memory (via U501) is controlled by the
output of U642 (diagram 7). This input to NAND-gate
U650B is a delayed version of the 4XPC (2 MHz) clock
(D24XPC).The 150 ns delay provided ensures that the AID
Converter output byte has settled before being written to
the Acquisition Memory.
must be ignored in order to maintain proper trigger loca-
tion within the complete record. The CCD Phase Clock
Array (U470) knows where the record trigger occurred
relative to the TTL1B pulse (1-of-32 position) and sends
this information to U670 on the TLO-TL4 (trigger location
bits 0 through 4) lines. This trigger-location number is
loaded into the counter and, as the samples are moved
out of the CCD array, that number of samples is essen-
tially discarded. Those samples are AID converted but will
not
be
stored because U650B is not yet enabled to gate
the SAVEACQ signal used to write the data into the
Acquisition Memory.
3-38
Since the trigger event can occur at anyone of the 32
analog samples that are taken between each TTL1B clock,
and since the Time Base Controller only keeps track of the
number of pretrigger and post-trigger samples in terms of
these 32-sample records, there are usually some samples
at the beginning of those in the CCD array B register that
are extra. When the analog samples are serially moved
out of the CCD array for digitization, these extra samples
When the delay requirements are met, the SYNTRIG is
allowed to occur when a trigger event occurs. The counter
then watches TTL1B to determine when the proper
number of post-trigger samples have been moved to the B
register to fill the post-trigger requirements, then it sets
SO (slow-out, pin 38) HI. This stops the sampling process
and starts AID conversion of the analog samples stored in
the CCD array B register.
A counter internal to U670 begins counting TTL 1B (TTL
version-Phase 1B) clocks to determine when at least
enough samples have been transferred into the "B" regis-
ter of the CCO arrays to fill "pretrigger" requirements.
Samples will then continue to be placed in the B register,
but no output samples will be saved until the record trigger
occurs. (All 1054 locations in the two sides of 16
X
33 B
register will fill if a record trigger does not occur before
that many samples have been taken.) Each TTL1B clock
represents 32 analog samples (two, 16-sample sides)
transferred into the CCO array B register. When the
proper number of pretrigger samples have been loaded,
U670 will set its EPTHO (end of pretrigger holdoff) line HI.
This signal enables Trigger Logic Array U370 (diagram 11),
and the state machine in Time Base Controller U670
starts watching the SYNTRIG (synchronized trigger) input
(pin 30) from the Phase Clock Array (U470, diagram 11)
for the "record" trigger. In the meantime, the Trigger Logic
Array will be counting delay clocks (DELCLK) to fulfill any
specified delay requirements before a record trigger is per-
mitted to be generated.
A state machine internal to Time Base Controller U670
runs the acquisition process from start to finish. When all
internal registers are properly loaded, the System JiP
writes to location 6022(h), generating a strobe that
switches acquisition control to the Time Base Controller.
This starts the acquisition system, and samples are taken
in the defined mode. For FISO operations, the following
occurs.
to dynamically control the acquisition circuitry in the
required mode and signal acquisition rate (set by a combi-
nation of FISO and SEL4/5). Writing to these "register"
locations also allows the System JiP to generate several
strobes for internal latching and control functions.
Theory of Operation-2430 Service
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