3-39
ROLL LOGIC. In ROLL mode the display is constantly
being updated as new data points are available.A means
is provided to tell the Waveform !1Pwhen new data pomts
are available. An interrupt to the Waveform !1P is gen-
erated by the Roll Logic flip-flop, U6518. When the
ACQUIREsignal from Time 8ase Controller U670 goes HI,
new waveform data points are acquired. The HI state of
that signal is clocked to the Q output of flip-flop U6518 on
the rising edge of the CE28/N signal; the same signal that
causes the sample data to be saved into the Acquisition
Memory in Short-Pipemode.The PTAVAIL signalat the Q
output is an interrupt to the Waveform !1P. When the
Waveform !1P services the interrupt request, it sets
PTACK (point acknowledge)LO via U5008 and U500C to
reset the flip-flop in preparation for the next new data
points. The saved points are also moved to the Save
Memory and then to the Display Memory for a display
update.
For non-envelopeacquisitions, ENVL is LO. The Set
input of flip-flop U651A is therefore asserted, and U651A
will be held in the Set state with the Q output (LOAD
LATCHES)held HI. That constant HI signal applied to the
Acquisition Latch Switching circuitry causes each data
point acquired to be loaded into the Acquisition Latches
and transferred into Acquisition Memory.
The Set input of U651A is HI during Envelope,the out-
put of the flip-flop is controlled by the DS23 clock and the
CE28/N clock (on the 0 input). The CE28/N clock is a
divided down DS23 clock, with the divisionfactor depend-
ing on the SEC/DIVsetting. The division factor determines
how many waveform samples will be compared for new
max and new min during each envelopesampling interval.
Only the maximum and minimum waveform data point
values that occur during the envelopesamplingintervalare
transferred to the Acquisition Memory.
LOAD LATCHES FLIP-FLOP.In Envelope Mode, Load
Latches flip-flop U651A puts out a signal at the beginning
of each envelope sampling interval that is HI for four
acquisition cycles. That HI LOAD LATCHES signal loads
the first four acquireddata points (two min-max pairs) into
the Acquisition Latches to be used for min-max com-
parison to the following waveform samples in that
Envelopesamplinginterval.
already is stored in Acquisition Memory, ACQDN is set.
Waveform data bytes are moved to the Save Memory by
the Waveform !1P and control is given back to the
System !1P.
Theory of Operation-2430 Service
Since CCD array samples are moved directly from the
input to the output via the first 8 register and since stored
samples may occur at a rate different than the sample
rate, pretrigger and post-trigger counting is done relative
to samples actually stored into the Acquisition Memory.
When enough valid pretrigger points have been saved,
EPTHO enables the Triggers. Data is saved in bursts of
two points (four points in ENVELOPEacquisition mode),
one for CH 1 and one for CH 2, at the synthesized rate.
When the trigger event occurs, the Trigger location bits
are set relative to the synthesizedclock and allow a data
correction algorithm to correct already-acquired data
points relative to the trigger event. Post-trigger sampling
occurs at the defined rate, and since
AID
converted data
To synthesize the sample rate for the Short-Pipe mode,
FISO (from U670 pin 36) is set LO by the System !1P,
thereby enabling the CE28/N (clock enable 28 divided by
N) input to U512C. The CE28/N clock (along with the
D
2
4XPC clock) then controls saving the waveform data
into the Acquisition Memory. In Short-Pipe mode, CCD
sampling occurs at a continuous 1 MHz rate, but due to
SEC/DIV setting data written to an internal counterin
U670, the synthesizedCE28/N clock will only allow every
"Nth" point to be saved in Acquisitionmemory to produce
only 50 data points per division in the display. Samples
between the saved Nth points are ignored. The syn-
thesized CE28/N clock will only enable U6508 long
enoughto save either two or four points and is dependent
on the sweep-rate division factor written to the internal
counter. This allows effectivesamplerates down to 1 sam-
ple every 2!1s (100!1s/div) to be achieved. The SOC
(slow-delay clock, U670-pin 29) runs at this effective
sample rate and allows the Trigger circuits to count delay
periodsin terms of sampleintervals.
SHORT-PIPE OPERATION. Short-Pipe operation is
similar to FISO in the way mode and setup data is loaded
and the way the internal counter is used to keep track of
various events. The major differences are: Short-Pipe
mode moves input samples directly from the CCD array
"A" register input, down the first "8" register channel and
out of the CCD array through the"C" register. Short-Pipe
mode must also synthesize the sample clock rate.
and U601). Since the Acquisition Memory addresses are
circular (incrementing the Address Counter from its last
address goes back to the first address), it knows the
record begins at the next address. With T82MEM LO, the
ACQ signal is routed through Mode Logic Switch U501 to
become the WP2MEM signal. The ACQ signal going LO
from the Waveform !1P via address decoder U570 enables
data buffer U610 to permit the Waveform !1Pto access the
waveform data stored in the Acquisition Memory (see
"Waveform Processor System" description).
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