The Record End Latch composed of U502 and U601
continually latches the address of the last Acquisition
memory location that was written. The latch is clocked on
the rising edge of the WE clock (from the SAVEACQ sig-
nal or the Waveform .uP WWR signal via Mode Logic
Switch U501) and provides the Waveform J.LPwith the last
address written (the end of the record for a full acquisition)
by the Time Base Controller or read by the Waveform J.LP.
Since the Acquisition Memory addresses are circular, the
start of a FISO record will always be the Record End
address plus one. In Short-Pipe mode, the Waveform .uP
will read those (two for normal, four for envelope) points
immediately preceding (and including) the Record End
address. The latched address (plus the trigger location
data) is placed on the Waveform .uPdata bus by asserting
RDMARO and RDMAR1 (read memory address) lines.
Record-End Latch
MEMORY INPUT BUFFER. Memory Input Buffer U613
applies the time-multiplexed waveform data bytes from the
Acquisition Latches (diagram 15) to the data inputs of the
Acquisition Memory inputs at all times except when the
Waveform J.LPis accessing the Memory. Inverter U620D
inverts the most-Significant bit of the sample data so that
range center of the AID Converter output corresponds to
00 hex (center screen value), thereby creating bipolar data
referenced to center screen.
Acquisition Memory
Acquisition Memory U600 is a random-access memory
device (RAM) that provides temporary storage of acquired
data points before they are moved into Save Memory.
Analog waveform samples from the CH 1 and CH 2 CCD
arrays are digitized and moved into Acquisition Memory
under control of the Time Base Controller (diagram 8),
alternating CH 1 data with CH 2 data. The Waveform J.LP
reads the data out of Acquisition Memory via buffer U610,
unscrambles it, and moves it to proper Save Memory
locations.
The TB2MEM signal from AND-gate U731D controls
the mode of the Acquisition Memory Address Counter
(composed of binary counters U300, U400, and U401).
When the the TB2MEM signal goes LO, the counters
become "transparent." This connects the Waveform .uP
address bus to the address inputs of the Acquisition
Memory so that the Address Counter output follows the
WAO-WAA (Waveform J.LPaddress bits O-A) lines. When
the TB2MEM signal is HI, the Time Base Controller is in
control of the Acquisition Memory, and counter will be in
its count mode as the acquired signals are being stored
into the Acquisition Memory.
3-40
The Address Counter increments the Acquisition
Memory address as each point is saved. Each write into
Acquisition Memory ends with the WE (write enable) signal
going HI, clocking the counter to address the next sequen-
tial Acquisition Memory location.
Address Counter
When the Waveform .uP wants to access the Acquisi-
tion Memory, it will set the ACQ line LO to enable its con-
trol signals to the inputs of Mode Logic Switch U501 and
wait for the ACQUIRE signal from Time Base Controller
U670 (diagram 8) to go LO (indicating that the Time Base
Controller is finished acquiring). When ACQUIRE goes LO,
the output of AND-gate U731D (TB2MEM) goes LO and
the Mode Logic Switch select the Waveform J.LPsignals to
control the Acquisition Memory. The LO TB2MEM signal
also sets the Address Counters to their Load state, and
the counter outputs then follow the WAO-WAA (Waveform
J.LPaddress bits O-A)lines, giving direct access to Acquisi-
tion Memory data locations by the Waveform J.LP.
With TB2MEM HI, the SAVEACQ signal from NAND-
gate U650B, is selected as the WE signal, and the OE is
set HI to disable the Acquisition Memory from outputting
data. Data buffer U613 is enabled by the LO level of the
EOE signal from pin 7 of the Mode Select Switch to con-
nect the the Envelope Logic Latch bus to the input bus of
the Acquisition Memory.
The WE (write enable) output from Mode Selector
Switch U501, pin 12, controls both writing into the Acquisi-
tion Memory and incrementing of the Address Counter.
With TB2MEM set LO, the WWR (Waveform J.LPwrite) sig-
nal gated through OR-gate U512D to the 4A input (pin 13)
of U501 controls writing to the Acquisition Memory. The
OE (output enable) derived from the Waveform .uP WRD
(Waveform J.LPread signal), controls the output of Acquisi-
tion Memory data. It is asserted LO only when the
Waveform J.LPis trying to read Acquisition Memory
locations.
The Memory Mode Control circuit is made up primarily
of Mode Selector Switch U501, a quad 2-to-1 multiplexer
that switches control signals between those of Time Base
Controller U670 and those of the Waveform J.LP.Selection
is done by the TB2MEM signal from AND-gate U731D
pin 11.
Memory Mode Control
In NORMAL mode, the ROLL signal is LO, and NAND-
gate U500B outputs a continuous logic HI that holds the
Roll Logic flip-flop in the Reset state (with the Q
output LO).
Theory of Operation-2430 Service
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