Common-mode signals are rejected from the trigger sig-
nal by the circuitry composed of operational amplifier
U230B and associated components. The inverting input of
U230B (pin 6) is connected to the common-mode point
between
+
PICK (pin 12) and - PICK (pin 15) of U420. Any
common-mode signals present are inverted and applied to
a common-mode point between R133 and R235 to cancel
the signals from the differential output. A filter network
composed of LR421 and a built-in circuit board capacitor
reduces trigger noise susceptibility.
A pickoff amplifier internal to U420 conditions the
trigger signal and provides the proper signal level at pin 15
to drive the AlB Trigger Generator (U150, diagram 11).
The pickoff point for the trigger signal is prior to the addi-
tion of the vertical-position offset, so the position of the
signal on the crt has no effect on the trigger operation.
However, the pickoff point is after the Preamplifier balance
and variable gain have been added to the signal, so both
of these functions affect trigger operation.
A user may change the Channel 1 variable gain by
pressing the CH1 VARIABLE button and pressing the
appropriate menu choice buttons. The Front Panel J.LP
detects these switch closures and reports them to the
System J.LP.The System J.LPmodifies the memory value
that is sent to the DAC System to reflect the user-defined
variable gain factor in the CH1-GAIN-CAL signal. The
memory value that is modified is the calibrated value
derived at the time of instrument self-calibration and
stored in nonvolatile memory. Selecting the CAL menu
choice, removes the variable gain modification and returns
the calibrated gain setting.
The voltage level of the CH1-PA-POS (Channel 1
Preamplifier Position) signal, from the circuit which
includes U630A and U630B (diagram 6), vertically posi-
tions the channel 1 trace. When the CH1 VERT POS con-
trol on the Front Panel is turned, the Front Panel J.LP
detects the change and reports it to the System J.LP.The
System J.LPincorporates the change and causes subse-
quent DAC System updates to reflect the new value in the
analog voltage level of the CH1-PA-POS signal.
sample-and-hold circuit formed by U641Band C648
(diagram 5). This signal is a de-offset level determined dur-
ing the auto-calibration procedure. The offset value is
stored as a calibration constant in nonvolatile memory
and, like the other DAC System outputs, is updated
approximately every 64 ms, holding the Preamplifier in a
dc-balanced condition.
3-42
Three analog control voltages set by the DAC System
circuitry (diagrams 5 and 6) modify the differential output
signal at pins 9 and 10 of the Preamplifier. CH1-BAL
(Channel 1 Balance) is applied to U420 pin 2 from the
Control data from the System J.LPis clocked into the
internal control register of U420 via pin 22 (CD) by the
clock signal applied to pin 23 (CC). This data causes the
Preamplifier either to multiply the normalized gain
(5 mV/div) by 2.5 or 1 or to divide the normalized gain by
2, 4, or 10. The resulting sensitivities are 2 mV/div,
5 mV/div, 10 mV/div, 20 mV/div, and 50 mV/div
respectively.
The Channel 1 vertical input signal is applied to pin A of
Channel 1 Preamplifier U420 via C1005, R1005, and
R1015. Resistor R1015 is a damping resistor, and the two
series diodes to the - 8 V supply, CR410 and CR411, pro-
tect the Preamplifier input from excessive negative volt-
ages. The differential Preamplifier signal outputs (+OUT
and - OUT) sink 12 mA of common-mode current from the
Channel 1 Peak Detector inputs and drive those 75 Q
inputs with a 0.25 mA per division output signal.
Channel 1 Preamplifier
Preamplifier U420 converts the single-ended input sig-
nal from the Channel 1 Attenuator to a differential output
signal used to drive the Channel 1 Peak Detector (U440,
diagram 10). The device provides amplification in
predefined increments, depending on the control data
written to it from the System J.LP.The Preamplifier also has
provisions for signal inversion, variable gain, vertical posi-
tioning, trigger signal pickoff, and balance control.
The MSB (most-significant bit) of the Attenuator Con-
trol Register, ATD15, is routed back to the System J.LPvia
CR287 and U380A (diagram 5), allowing diagnostic read-
back of the register contents.
To set the seven remaining Attenuator and coupling
relays, the sequence just described is repeated seven
more times. Whenever the System J.LPis informed by the
Front Panel J.LPthat the attenuation factor or input cou-
pling has changed, the entire relay-setting procedure is
repeated for all eight relays.
output of either U221 or U511 to close the selected con-
tacts. Once set, the magnetic-latch feature will hold the
relay set to this position until opposing data is clocked into
the Attenuator Control Register and strobed into the relay.
All coil leads for the remaining relays are set HI, and only
the selected relay will be set.
Theory of Operation-2430 Service
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