3-43
CCD/Clock Drivers U350 and U450 are hybrid devices
containing a charge-coupled device (CCD) integrated cir-
cuit and a Clock Driver integrated circuit. The charge-
coupled devices are very fast analog shift registers.
Differential signal level applied to the inputs of the CCD
from the Peak Detectors are sequentially clocked into the
CCD registers at the processor-selected sample rate as
determined by the SEC/DIV switch setting. Movement of
the analog samples through the CCD arrays is controlled
by the Clock Driver circuitry of the devices. Shifting the
samples out of the CCD to be digitized in done with the
combined clocking action of the internal Clock Drivers and
the clock signals supplied externally to the CCD via Q450,
Q460, Q550, Q551, and Q560. All control logiC for the
CCD/Clock Drivers, with the exception of the RESET sig-
nal from the System Clock circuitry (diagram 7), is derived
from Phase Clock Array U470 (diagram 11).
Peak Detectors U340 and U440 are hybrid devices hav-
ing two modes of operation: "track" and "peak detect."
For NORMAL and AVG (average) acquisition modes, the
Peak Detectors track the input signal and provide signal
gain from the Preamplifiers to the CCD arrays. In the peak
detect mode used for ENVELOPE acquisitions, the Peak
Detectors detect and hold the most positive and the most
negative amplitude value of the input signal that occurs
during each sampling interval. The peak values are
amplified as in the NORMAL and AVG modes and applied
to the input registers of the CCD arrays in such a manner
as to produce a composite waveform of the most positive
and most negative waveform amplitudes.
The Peak Detectors and CCD/Clock Driver arrays
(diagram 10) form what is essentially a very fast analog
shift register. Waveform samples from each Preamplifier
(U320 and U420, diagram 9) are loaded into the shift regis-
ter array at a selected sample rate up to 10 ns per division
and clocked out of the array at a slower fixed rate for
digitization by the AID Converter (diagram 15).
PEAK DETECTORS AND
CCD/CLOCK DRIVERS
Dc offsets in the output signal due to any tracking
differences between the +5 V and the - 5 V supply to
U100 are reduced by the Tracking-Regulator circuit com-
posed of U120, Q110, and associated components. Opera-
tional amplifier U120 and Q110 is configured so that the
output voltage at the emitter of Q110 follows the - 5 V
supply applied to R210. This tracking arrangement
ensures that the supply voltages are of equal magnitude to
minimize dc offsets in the output signals.
Theory of Operation-2430 Service
External trigger signal sensitivities may be set by the
user to allow triggering ranges of either
±
0.9 volts (EXT
-:- 1) or
±
4.5 volts (EXT
-i-
5). Larger applied voltages on
the external trigger inputs will exceed the control ranges of
the Trigger System. The logic levels of control bits applied
to U100 pin 30 (GA3) and pin 31 (GM) from Source Select
Control Register U140 (diagram 5) set the gain of the
EXT 1 and EXT 2 Preamplifiers respectively.
External Trigger Preamplifier
The functions provided by External Trigger Preamplifier
U100 are similar to those provided by the Channel 1 and
Channel 2 Preamplifiers. The single-ended EXT TRIG 1
and EXT TRIG 2 input Signals are buffered by U100 and
routed to A/B Trigger Generator U150 (diagram 11) where
they are available for selection as the trigger source for
either the A or B trigger signal.
The amplified Channel 2 +PRTR signal from U320
pin 11 provides an accurate representation of the Chan-
nel 2 signal at the rear-panel CH 2 OUT connector. The
+
PRTR pickoff signal is applied to the emitter of Q240B
via a voltage divider formed by R234, R241, and R240.
Transistor Q240B, configured as a diode, provides thermal
compensation for the bias voltage of Q240A and reduces
dc level shifts with varying temperature. Emitter-follower
Q240A provides the drive and impedance matching to the
CH 2 OUT connector and removes the diode drop added
by Q240B. Clamp diodes CR140 and CR141 protect
Q240A should a drive signal be accidentally applied to the
CH 2 OUT connector.
Channel 2 Preamplifier
Operation of Channel 2 Preamplifier U320 is nearly
identical to that of the Channel 1 Preamplifier just
described. The exceptions are that the signal obtained
from the pickoff reverse-termination return (pin 11) is used
to drive the rear-panel CH 2 OUT connector and that the
signal from the positive trigger pickoff (pin 12) is used to
drive the Video Option Back-Porch Clamp circuit
(diagram 21). The output of that clamp circuit is an offset
signal, applied to the Channel 2 Preamplifier at pin 3, that
is used to remove ac power-supply hum from the display
of a video signal applied to the Channel 2 input when the
Video option is in use.
The drain voltage for the input FET of the Preamplifier
is provided by the circuit composed of VR420, R512,
R515, and R516. Resistors R516 and R515 are part of the
self-calibration circuitry and are used to match the gain of
the CH1-BAL signal (pin 2) with that of the output of the
attenuator.
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