Common-Mode Adjust
The Common-Mode Adjust Circuits (US40A and B,
OS40, 0640, and associated components) allow varying,
under control of the System f.LP,the common-mode volt-
age levels at the output of the CH 1 Peak Detector. (Simi-
lar circuitry performs the same task for the CH 2 Peak
Detector.) Adjusting these dc levels changes the gain of
the CCD and is done during self-calibration to control the
overall gain of the Peak Detector-CCD subsystem. The
CH 1-0UT1 Common-Mode Adjust circuit is described;
the remaining Common-Mode Adjust circuits operate
identically.
The +CAL and - CAL inputs at pins 8 and 10 are
identical to the signal inputs, but they are used only for the
application of test signals during calibration or diagnostic
testing. Selection of the inputs is controlled by the
CAL/SIG signal. The test signals applied to pins 8 and 10
from the DAC System are used for testing and calibrating
the Peak Detectors, the CCD/Clock Drivers, the CCD Out-
put circuits, and the A/D Converter.
DC offsets between the internal peak detectors of U440
are nulled out by voltage levels applied from the DAC Sys-
tem (diagram 6) to pins 27 and 34. Bias current for the
input stage of U440 is set by R430 on pin 47, and output
stage bias is set by R440 on pin 32.
Peak detect mode for ENVELOPE acquisitions is turned
on by setting PO LO at pin 21 and SLOW/FAST HI at
pin 22 of Peak Detector U440. The differential ECL peak-
detector clock signals (PD1 and PD2) toggle under control
of the Phase Clock Array (U470, diagram 11) to control
the internal peak detector switching and multiplexing of
the positive and negative peaks to the OUT1 and OUT3
stages. The table in Figure 3-4 shows timing of the peak
detector clocks and illustrates how alternate peaks are
applied to the SIG1 and SIG3 inputs of the CCD.
For NORMAL and AVERAGE acquisition modes, the
Peak Detector operates in the track mode. To track the
input signal and supply buffering only to the input signal,
pin 21 (PO) is set HI and pin 22 {SLOW/FAST is set LO,
and the differential peak-detector clock signals (PD1 and
PD2) are held at fixed levels (PD1 LO and PD2 HI). These
control state levels set up one of the fast-peak detectors
in the positive- and negative-peak detectors to follow the
input signal in the track mode. The differential outputs at
OUT1 and OUT3 follow the input signal at a signal level of
400 mV/division with a dc common-mode voltage of about
9 V. The CCD/Clock Driver SIG1 and SIG3 inputs are high
impedance, so output loading of the Peak Detectors is
provided by the Common-Mode Adjust circuits (discussed
later).
3-44
The differential signal from the CH 1 Preamplifier is
applied to the CH 1 Peak Detector (U440) on input pins 4
and 6. In ENVELOPE acquisition mode, two sets of two
fast-peak detectors following the input stage are used to
permit continuous peak detection of negative and positive
peaks of the input signal. While the PDA fast-peak detec-
tor is peak detecting the positive peak, the PDB peak
detector is holding the last peak or resetting and vice
versa (see table in Figure 3-4). Each of fast-peak detectors
is followed by a slow-peak detector to increase the peak-
hold time to the CCD input register. The outputs of the
positive peak detectors are multiplexed to the differential
OUT1 pins (pins 26 and 28) while the outputs of the nega-
tive peak detectors are multiplexed to the differential
OUT3 pins (pins 33 and 3S).
Two user-selectable bandwidth limiters provide
bandwidth reductions to either 20 MHz or SOMHz for the
signal through the Peak Detectors. With the Video Option
installed, one of the 20 MHz limiter coils (LS31 for CH 1) is
adjustable to optimize the 20 MHz response for video sig-
nal operation. Without the option, both 20 MHz bandwidth
limit coils for each Peak Detector are fixed values. Fifty
megahertz bandwidth is adjusted by C431 for CH 1. The
input stage of the Peak Detector is where bandwidth limit-
ing is switched. Three bandwidth-select bits (FULL, BWSO,
and BW20) applied from the Peak Detector Control regis-
ter (US30,diagram S)control the bandwidth. Only one con-
trol bit at a time is set HI, and that bit controls the input
amplifier bandwidth accordingly.
The Peak Detectors provide peak detection, gain, and
buffering of the CH 1 and CH 2 signals. Peak detect is
enabled for ENVELOPE mode acquisitions only, but signal
buffering is provided for all modes. Operation of both Peak
Detectors is the same; therefore, the description is limited
to the CH 1 circuitry. A simplified block diagram of the
Peak Detector is shown in Figure 3-4.
Peak Detectors
Signal samples from both vertical channels are continu-
ously loaded into and shifted through the CCD arrays until
a trigger event occurs. The Time Base Controller (U670,
diagram 8) then allows a specific number of further analog
samples to be shifted into the arrays depending on the
number of post-trigger samples needed to fill the
waveform record. That number is determined by the TRIG
POSITION setting for the acquisition. When the necessary
samples have been loaded into the arrays, sampling is
halted. The differential analog samples stored in the CCD
arrays are then shifted out of the CCD to the CCD Output
circuitry (diagram 14) where they are conditioned and mul-
tiplexed to the A/D Converter to be digitized.
Theory of Operation-2430 Service
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