The Short Pipe mode of the CCO is in effect at
SEC/OIV settings of 100 ILS and slower. The CCOis
operated at a continuous 500 kHz rate. Samples are
In FISO mode, 16 samples are shifted down the serial
input A register at a clock period equal to 0.04 times the
SEC/OIVsetting. On every Sixteenthclock cycle, the posi-
tive 2A clock pulse is replaced by a single positive pulse
that moves all the charge packets into a transfer-in regis-
ter at the head of the 8 register array. The A register is
then empty and ready to accept new serial-in samples.
The 8 register clocks run at 1/16 the speedof the A regis-
ter clock rate so that the A register will be filled prior to
each 8 register clock. In this way, the 8 register is filled
with samplesthat are moved in parallelthrough the array.
Ouring this Fast-In portion of theinput cycle, unneeded
chargesthat arrive at the output C register due to the way
that the input signal is continually sampled (until a trigger
occurs) are emptied from the CCO through the output
diffusion (001). When the Time 8ase Controller deter-
mines that the proper number of samples have been
stored in the CCO after the trigger occurs, the mode
changes to SlOW-Out.The C register and RESET clocks
then toggle at a constant 500 kHz rate to shift samples
out of the CCOto be digitized.
An extra input gate is addedto Side3, the other side of
the CH 1 CCO array (not shownin Figure3-5) to accept
the Side3 charge packets and permit their movement
through the CCO to be synchronizedwith the Side 1 sam-
ples. The S3 Sample clock (opposite in polarity to the Sl
Sampleclock) performs the samplingfunction of the SIG3
signal. This samplingschemedoubles the effective sample
rate of the CCO. Thus, the 100 megasampleper second
sampling rate is achieved with 50 MHz"A" register
clocks. All register gates are driven with bipolar square-
wave signals of + 5 V to - 5 V. The RESET clock signal
also switches between+5 V and -5 V, but it is HI for
only 200 ns of the total 2ILSperiod.
All the registers require four-phase gate clocking to
move the sample charge packets through the CCO.
Hence,there are four"A" register clocks, four "8" regis-
ter clocks, and four "C" register clocks. There is also a
Transfer In (TI) clock to shift samples from the serial A
register into the 8 register and a Transfer Out (TO) clock
to move them from the 8 register to the C register. The
RESET clock discharges the output wells between output
sample intervals so that charge does not accumulate at
the input to the source-follower output amplifier. The Sl
Sample clock samples the analoginput signal at the side
one inputs. Samplingoccurs on the falling edge of Sl, and
the charge packet representing the instantaneous analog
signal valueis initially formed under the first "1A" gate
(the first gate that is driven by the A register Phase1
clock).
3-46
A simplifieddiagramof one-halfof one CCO is shown in
Figure3-5. The half shown, the SIG1 side or Side 1, is
nearly identicalto the SIG3 side (Side3) of the CCO.Each
side provides temporary storage of 528 analog samples
for a total storage of 1056 samples of a single channel.
The extra samples above that needed for the 1024-byte
waveform record are neededfor proper clock switching
between the Fast-In and Slow-Out portions of the FISO
cycle. The CCO has a Serial-Parallel-Serial(S-P-S) archi-
tecture. Each side has a 16 sample serial input"A" regis-
ter, a 16 X 33 sampleparallelstorage"8" register, and a
16 sample serial output "C" register. Two such SPS sec-
tions are shown in Figure3-5.
Charge-Coupled Devices (CCO)
The CCO portion of the CCO/Clock Oriver hybrid is a
MOS-type integrated circuit that functions as a very fast
analog shift register. A signal applied to the input is sam-
pled by being converted to charge packets. These charge
packets are then shifted through the CCO registers by
MOS-circuit gating at intervals determined by the clock
rates applied by the Clock Oriver integratedcircuit portion
of the hybrid.The internal arrangementof the CCOanalog
shift registers and the total amount of storage space per-
mits the input signal to be sampled at a high clock rate
when necessary for the higher frequency signals. The
charge packet samples are temporarily stored and then
shifted out of the CCO at a much slower rate than the
samplingrate. An inexpensiveA/O Converter can be used
to digitize the signal and slower memory circuits used to
store the digitizedsamples.This type of operation is called
Fast-In-Slow-Out(FISO) and is used at SEC/OIVsettings
of 50 ILSand faster. At SEC/OIV settings of 100 ILSand
slower, the CCO runs with a constant clock rate of
500 kHz in a mode calledShort Pipeline(discussedlater).
The
oun
+ and OUT1- common voltage is level
shifted and attenuated, then applied to U540A pin 3.
Operationalamplifier U540A compares the common-mode
level with the attenuated CM11 level from the OAC Sys-
tem. The output of U540A drives 0640 to supply more or
less current to the collector circuit thus raising or lowering
the voltage on pin 25 of U440. Common-modecurrentis
drawn by pins 26 and 28 via R540C and R4500 to com-
plete the feedback loop to the operational amplifier. Addi-
tional currentis drawn by VCC1 (pin 25), part of which is
supplied via R651 to reduce the stress on 0640. Emitter
resistor R647 provides protection to 0640 against exces-
sive current demand in the event of a short or overload.
Resistors R647 and R651 also limit the voltage gain of
0640 to stabilize the feedback loop of the Common-Mode
Adjust circuit.
Theory of Operation-2430 Service
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