Since the input to the A/D Converter is time multiplexed
between CH1 maximum, CH2 maximum, CH1 minimum,
and CH2 minimum values from the Peak Detectors, the
latched data applied to the Magnitude Comparator from
the Max/Min Latches must also be time multiplexed to
maintain the correct relationship for making the compari-
sons (CH1 maximum against CH1 maximum, CH1
minimum against CH1 minimum, etc.). The necessary time
multiplexing is done by the Envelope Latching Logic
circuitry.
Envelope Min-Max Comparator
For ENVELOPE Mode acquisitions, glitch-catching at
the slow SEC/DIV settings is done by the Envelope Min-
Max Comparator circuit formed by four-bit comparators
U740 and U732. At SEC/DIV settings slower than 50
J..LS,
analog Peak Detectors U440 and U340 provide more sam-
ples than needed to fill the required 50 data points (25
min-max pairs) per division, so not all are saved. During
each envelope sampling interval (1/50 of the SEC/DIV set-
ting at 50
J..L S
and slower), the Min-Max Comparator com-
pares every Peak Detector min/max value from A/D Con-
verter U560 to the last-latched maximum or minimum byte
to determine which sample will be saved. If the new byte
value is greater than the latched byte value, the MAX out-
put of Comparator U732 (pin 5) will go HI; if less than the
latched value, MIN at pin 7 will go HI. If the A/D output
value is equal to the latched value, both connected out-
puts of Magnitude Comparator U732 will remain LO. The
final min byte and max byte obtained from each channel
during an envelope sampling interval are saved to the
Acquisition Memory as part of the envelope waveform
record.
The input sample is converted on the falling edge of
D24XPC, a 2 MHz clock signal. A valid data byte
representing the analog input voltage appears on the A/D
Converter output approximately 20 ns later. That data
byte is applied to the 8-bit Magnitude Comparator formed
by U740 and U732, with the four LSB going to U740 and
the four MSB of the byte going to U732.
The A2D REF voltage (-0.5 volt) is amplified and
inverted by U880 to produce the 2 V reference voltage
used by the A/D Converter. Noise and ripple are filtered
from the amplified reference voltage by L770, C560, and
C776. The negative side of the reference is tied to ground;
therefore, input voltages for conversion may range from
o
V to + 2 V. The time-multiplexed CCD Data signal
current develops a voltage across R880 that is offset by
the A2D REF and then amplified and inverted by U780 to
produce an input signal to the A/D Converter within the
o
V to +2 V range needed. The amplified signal is applied
to the analog input of U560 after being filtered by L780
and C770.
3-60
AID
Converter
A/D Converter U560 is an 8-bit flash converter that digi-
tizes the analog samples from the CCD arrays at an
overall conversion rate of 2 MHz. (See the partial diagram
15 in the Diagrams section for instruments with serial
numbers below BOll146.)
The A/D Converter and Acquisition Latches
(diagram 15) circuit consists of eight-bit A/D Converter
U560, eight-bit Min-Max Comparator U740 and U732 (for
ENVELOPE acquisitions), Acquisition Latches U631, U632,
U630, and U640, and latch switching circuitry to direct and
latch the acquired data point values.
AID CONVERTER AND
ACQUISITION LATCHES
Secondary Supplies
The Secondary Supplies circuit, composed of U861A,
U861B, UB61C, U861D, and associated components, pro-
vides operating voltages used by the CCD Output circuitry.
The voltage level ofthe A2D REF (- 0.5 V analog-to-digital
reference) is determined by the current through RB61 from
operational amplifier UB61C and is set by the resistive
divider string formed by R762, R763, and R764 from the
+ 10 VREF supply. The other voltage outputs (+ 7.5 V and
+ 9 V
RA
and + 9 V
RB)
are set by the various taps on the
resistive voltage divider and buffered by operational
amplifiers.
Precise current matching of the Side 1 and Side 3 sig-
nal offsets is achieved by setting the DAC-generated
CENTER 1 voltage at the time of calibration. Similar offset
matching for CH 2 is done with the CENTER 2 signal.
Selection of the CH 1-Side 1 current signal to be digi-
tized by the A/D Converter is controlled by the DS11 (Data
Select-Channel 1-Side 1) line. As shown in Figure 3-3,
only one of the four DS signals will be LO at any time. A
LO DS11 signal applied to the base of Q770 will turn that
transistor off. The other transistor of CH 1 (QB70) and
both of the CH 2 transistors (Q7BOand QBBO)are on to
shunt their associated signal currents to ground. Each of
the four shunting transistors will be turned off in sequence
to allow its associated signal current to pass to the CCD
DATA node via a series common-base transistor (Q772 for
Channell-Side 1). The resulting CCD DATA signal is a
time-multiplexed combination of all four CCD output chan-
nels (two from CH 1 and two from CH 2).
The level stored on Hold capacitor C561 is buffered by
operational amplifier U770B. The operational amplifier,
along with Q771, converts the applied input sample volt-
age to output current.
Theory of Operation-2430 Service
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