3-61
The Display and Attributes Memory (diagram16) is
where the Waveform Processor stores waveform and
readout data that is to be displayedon the crt. Digital-to-
Analog converters (DAC), under control of the Display
Control circuits, convert this stored data to the vertical-
and horizontal-deflection signal currents that drive the
DisplayOutput amplifiers.
DISPLAY AND ATTRIBUTES MEMORY
Acquisition Latches
During EnvelopeMode, the Acquisition Latches perform
as Min-Max latches (U631 and U632 Max; U630 and
U640 Min) to hold the maximum and minimum data point
values being comparedduring the samplinginterval.These
values are compared to each newly converted waveform
sample to determine when new maximums or minimums
occur. Output enablingand data latching are controlled by
the AcquisitionLatch Switching as previouslydescribed.
When the 4XPC (2 MHz) clock occurs, the enabled
clocking flip-flop transfers the level at its D input to its
Q
output. If that level is a HI (a new max has been found),
the current
AID
Converteroutput data byte (the new max)
will be latched into the associated Max Latch (either U632
or U631, dependingon whether it is CH 1 or CH 2 data),
where it then becomes the new comparison level. MIN
clocks are produced by U510B and U511A in a similar
fashion, latching the new MIN values into either U640
or U630.
When the Envelope Min-Max Comparator detects that
the
AID
Converter output byte value is either above or
below the latched byte value, the MAX or MIN output of
U732 will go HI respectively. The HI is passed through
U512A (MIN) or U512B (MAX) to the D inputs of flip-flops
U510 and U511. Since the
AID
Converter output byte
value could represent any of the four CCD array channels,
the data select lines that determine what sample is
currently being output from the CCD arrays are appliedto
the reset inputs of U510 (A and B) and U511 (A and B).
Only that clocking flip-flop corresponding to the selected
data sample is enabled by a HI data select line; all others
remainin the RESETstate.
control output enabling of the four latches, causing the
Acquisition Latch corresponding with the selected CCD
output (CH 1 or CH 2, maximumor minimum)to apply the
previously latched data byte to the inputs of the Envelope
Min-Max Comparator.
AID
Converter output data is thus
always being compared to the proper maximum or
minimumdata value.
Theory of Operation-2430 Service
As in NORMAL Mode acquisitions, output enabling of
the four latches is controlled by the DS11, DS13, DS21,
and DS23 data select lines. The
Q
outputs of the flip-flops
The Acquisition Latch Switching circuitry multiplexes
the latched CH 1 and CH 2 maximum and minimumdata
bytes to the inputs of the EnvelopeMin-Max Comparat~r
so that each digitized sample from the
AID
Converter
IS
comparedto the correct previoussample(CH 1 Min to the
previous CH 1 Min, etc.). It also provides the proper ena-
bling and clocking to direct a new maximum or minimum
data bytes into the correct AcquisitionLatch.
ENVELOPE MODE ACQUISITIONS.
In ENVELOPE
MODE, the LOAD LATCHES signal input to U512A and
U512B (from the Time Base Controller, diagram8) forces
each clock flip-flop in turn to clock the
AID
Converterout-
put data byte into its associated latch by holding their D
inputs HI during the first four data point conversions in
each envelopesampling interval. These first four samples
(one byte in each Acquisition Latch) initialize the min/max
data in the latches for comparison to the remainingdata
samplesthat occur in the envelopesamplinginterval.
Output enablingof the four Acquisition Latches is con-
trolled by the DS11, DS13, DS21, and DS23 data select
lines, which also control the multiplexingof the CCD ana-
log samples to
AID
Converter U560. The states of these
select lines, only one of which may be HI at a time, are
latched into the four flip-flops of U520 and U521 by the
20 MHz system clock (C20M1).The
Q
outputs of the flip-
flops control output enabling of the four Acquisition
Latches.One at a time, their outputs are enabledto apply
the acquired data point to the output bus for transfer to
the Acquisition Memory input buffer (U613, diagram8).
Two hundred and fifty nanoseconds after one of the
Acquisition Latches has been enabled, the rising edge of
the 4XPC signal clocks the HI state present on the D
inputs of the flip-flops of U510 and U511 to the
Q
output
of the enabled flip-flop. That rising edge then clocks the
data byte from the
AID
Converter through the enabled
Acquisition Latch to the input buffer of the Acquisition
Memory.
Acquisition Latch Switching
NORMAL MODE ACQUISITIONS. In
non-envelope
mode, the LOAD LATCHES signal from the Time Base
Controller remainsin its
HI
state. With LOAD LATCHES
HI
at one of the inputs of OR-gates U512A and U512B, the
MIN and MAX signals from the EnvelopeMin-Max Com-
parators are ignored, and the outputs from the gates are
held HI. This causes each sample from the
AID
Converter
to be clockeddirectly through the AcquisitionLatches.
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