For normal waveform displays, vertical deflection data
may come from either the Vertical or the Horizontal
Display RAM. To route data from the Horizontal RAM to
the Vertical DAC, the outputs of the Vertical RAM will be
disabled(OEY),the outputs of the Horizontal RAM will be
enabled (OEX goes LO), and buffer U320 will be enabled
(XTOVERT goes LO). These three signals are all con-
trolled by the System lIP by writing bits XON and XTO-
VERT HI into Mode Control Register U541 (diagram17)
Horizontal Data Buffers
The Horizontal Data Buffers, U320 and U321, are used
to route the data from the Horizontal RAM to either the
Horizontal DAC or the Vertical DAC, depending on the
type of display beingproduced.
When displaying data from either (or both) the Vertical
RAM or Horizontal RAM (the addresses applied to all
three RAM chips are the same),the attribute data for each
data point will be appliedto the Z-Axis circuitto determine
the intensity of each point. A HI bit from the DOoutput of
U430will intensifythe displayedpoint.
To read attribute data out of the RAM, the Waveform
lIP sets WRD LO. This LO, along with the address-
decoded DATT (attribute data) line, enables buffer U423A
and placesthe addressedoutput bit from the DOoutput of
U430 onto bit WD7 of the data bus.
The write enable of the Attribute RAM (WRA) is gated
by U422C between 12K and 14K when DATT is LO from
decoder U570 (diagram17). WRA going LO enables the
data from bit WD7 of the data bus to be written to the
addressedlocation. Gate U422A prevents the WWR clock
from being gated to U422C if the Display Counter is
selected(WaveformlIP not in control of the addressbus).
Attributes RAM
Attributes RAM U430 contains 4KX 1 points of data
that tell the Z-Axis system (using the BRIGHTZ signal)
whether or not a data point read from either the Vertical
Display RAM or the Horizontal Display RAM should be
intensified. Operation of the RAM is similar to that just
described for the Vertical and Horizontal RAMs except
that the data path is only one bit wide.
Data that may be stored in the Horizontal Display RAM
includestwo 512-point waveforms and 1K X 8 of readout
information. During a waveform display, the data output
from the Horizontal RAM may be routed to either the Vert-
ical DAC or Horizontal DAC, providingfor either two more
YT displaysor two XY displays.
3-62
Horizontal Display RAM
Operation of Horizontal Display RAM U440 is identical
to that of the Vertical Display RAM just described. The
Horizontal RAM chip select (CSX)is gated through U323D
for addresses between 10K and 12K when DISP is LO.
If the Waveform lIP needs to read data from the Verti-
cal Display RAM, it outputs an address within 8K to 10K
addressspace of the RAM. This address blockis decoded
by U323B to enable both the Vertical Display RAM(via
U421A) and bus transceiverU322. Since the WaveformlIP
is trying to read data, its WRD (waveform processorread)
line will be set LO. This enables the RAM outputs via
U323C and U421B and causes buffer U322 to direct the
data onto the WaveformlIP data bus.
To display the stored data points, the SystemlIP loads
the starting address of the data block to be displayedinto
the Display Counter and selects the Display Counter to
address the Vertical Display RAM (via the Address Multi-
plexer).The System lIP also sets the YON (verticaldisplay
on) bit applied to U421A and U421B LO, selecting the
Vertical Display RAM and enablingits outputs. As the
Display Counter increments,the selected block of data is
sequentiallyclocked out onto the DY bus (vertical-display
data bus) and applied to Vertical DAC U142 to produce
the vertical deflection signal current to the Vertical Output
Amplifiers.
To write data into the Vertical Display RAM, the
WaveformlIP puts the data byte to be written onto its WD
bus and sets its WRD (waveform read) bit HI. This HI
enables bus transceiver U322, and the vertical data is
appliedto I/O (in/out) pins of the RAM. At the same time,
the DISP signal is address decoded LO (from decoder
U570,diagram2) for addressesbetween8K and 12K, and
the WAB address bit appliedto U323B selectsthe Vertical
RAM U431 via U421A. When the WaveformlIP generates
its write pulse (WWR),it is transmitted through U422A and
U422D, writing data into the Vertical Display RAM. This
process occurs for each data byte (point) of waveform
information.
Vertical Display RAM
Vertical Display RAM U431 stores the vertical-
deflection data for four 512-point waveforms. Data points
to be displayedare written from the Save Memoryinto the
RAM by the Waveform lIP (diagram2) on the WD bus
(waveformdata bus) via bus transceiver U322.The stored
waveform display bytes are read sequentially out of the
Vertical Display RAM in blocks under control of the
Display Counter (diagram17) and applied to Vertical DAC
U142to producethe analogvertical deflectionsignalof the
displayedwaveform.
Theory of Operation-2430 Service
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