3-63
For "directed-beam" cursors, such as the "+" made
up of individual microprocessor-directed points displayed
on screen, both cursor registers are enabled after the Sys-
tem ~p writes one dot of XY position data into the regis-
ters. To display the addressed point, the processor sets
the HZON (host z-axis on) bit in the Misc Register LO,
then HI. The processor then calculates the next point of
the "+", writes the position data to the cursor registers,
enables the registers, and sets HZON LO to display that
point. This cycle continues until the entire" +" is drawn.
Time Cursor Register
Time Cursor Register U441 provides a function similar
to the Volts Cursor Register. Time-cursor data is written
to the register from the system processor on the rising
edge of the address-decoded TCURS clock (time-cursor
clock). This data is applied to Horizontal DAC U250 (along
with the DXO-DX1 bits from the Misc Register) to define
the horizontal position of the cursor. A software ramp pre-
viously written into Vertical RAM U431 is applied to Verti-
cal DAC U142 as the Display State Machine runs (started
in the same way as the volts-cursor display).
Volts-cursor displays are a special type of "waveform"
display wherein the vertical deflection data from the Verti-
cal Display RAM is disabled (by turning off the RAM chip
select), and the data bits in Volts Cursor Register U241
(and the DYO-DY1 bits from the Misc Register U540,
diagram 17) are applied to Vertical DAC U142 instead.
Cursor display is automatically selected by the Z-Axis logic
when neither WFM nor RO are asserted (not a waveform
display and not a readout display). To start the display,
the System ~p asserts the START bit in the Display Con-
trol Register as it would for a waveform display, starting
the Display State Machine. The result is a horizontal line
displayed on the screen at the level set by the data from
the Volts Cursor Register. When displaying cursors on a
waveform, the two LSBs from the Misc Register are set to
0, decreasing the resolution from 1024 levels to 256 levels.
Volts Cursor Register
Volts Cursor Register U241 is an address-decoded
memory location where the System ~p writes the eight
MSBs of the vertical-position data for volts-cursor
displays. Data written into this register, along with two bits
written into the Misc Register U540, define the vertical
position of the Volts cursor. Since volts-cursor displays
have two cursors, the microprocessor alternately writes
the position data for each cursor into the registers just
before it is displayed. Data is written into the register on
the rising edge of the address-decoded VCURS clock
pulse.
Theory of Operation-2430 Service
Ramp Buffers
Ramp Buffers U130 and U140 apply the ten LSBs of
the Display Counter address (via Address Multiplexer
U210, U212, and U221 on diagram 17) to the Horizontal
DAC during YT waveform (non-XY) displays. Since the
Display Counter address is merely incrementing for
waveform displays, a horizontal ramp results at the Hor-
izontal DAC outputs. Each sequentially acquired data point
is thus displayed at its corresponding horizontal (time-
dependent) address on the crt. The buffers are enabled by
the COUNTEN (counter enable) bit from the Mode-Control
Register.
The six LSBs are applied to the six MSBs of the Hor-
izontal DAC and are used to select one of the 64 possible
character positions on the selected readout line. Since a
maximum of only 40 characters will actually be displayed
on any given line, the gain of the Horizontal Output
Amplifier increases when readout is being displayed. The
center 40 character positions then fill the display horizon-
tally. This action is more fully explained in the Horizontal
Output Amplifier description.
Four of these bits, 06-09, are applied to the four most
significant bits (MSB) of the Vertical DAC input through
U140A and are used to select one of the 16 available
readout lines for the selected character to be displayed on.
Readout Buffers
Readout buffers U240 and U140 direct the ten least
significant bits (LSB) from the Display Counter to the Hor-
izontal DAC and the Vertical DAC during readout displays.
The buffers are enabled by a LO RO signal at their enable
inputs.
During readout displays, both U320 and U321 will be
disabled, along with the Vertical RAM. Since the readout
character-code data is stored in the Horizontal RAM, it will
be enabled. Character-code data from the Horizontal RAM
is output to the Readout State Machine, where it is con-
verted to the appropriate horizontal- and vertical-deflection
codes.
For XY displays, Mode-Control bits XON, YON, and XY
are set HI while XTOVERT is set LO. This applies
addressed data from the Vertical RAM to the Vertical DAC
and applies the addressed data from the Horizontal RAM
to the Horizontal DAC via now-enabled buffer U321. A
waveform versus waveform (XY) display results.
and writing a LO to the YON output of the register: Now,
data addressed in the Horizontal RAM is applied to the
Vertical DAC to produce vertical waveform deflections.
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