Terasic DE10-Lite - Page 39

DE10-Lite
User Manual
38
www.terasic.com
May 11, 2018
Table 3-12 Pin Assignment of SDRAM
Signal Name
FPGA Pin No.
Description
I/O Standard
DRAM_ADDR0
PIN_U17
SDRAM Address[0]
3.3-V LVTTL
DRAM_ADDR1
PIN_W19
SDRAM Address[1]
3.3-V LVTTL
DRAM_ADDR2
PIN_V18
SDRAM Address[2]
3.3-V LVTTL
DRAM_ADDR3
PIN_U18
SDRAM Address[3]
3.3-V LVTTL
DRAM_ADDR4
PIN_U19
SDRAM Address[4]
3.3-V LVTTL
DRAM_ADDR5
PIN_T18
SDRAM Address[5]
3.3-V LVTTL
DRAM_ADDR6
PIN_T19
SDRAM Address[6]
3.3-V LVTTL
DRAM_ADDR7
PIN_R18
SDRAM Address[7]
3.3-V LVTTL
DRAM_ADDR8
PIN_P18
SDRAM Address[8]
3.3-V LVTTL
DRAM_ADDR9
PIN_P19
SDRAM Address[9]
3.3-V LVTTL
DRAM_ADDR10
PIN_T20
SDRAM Address[10]
3.3-V LVTTL
DRAM_ADDR11
PIN_P20
SDRAM Address[11]
3.3-V LVTTL
DRAM_ADDR12
PIN_R20
SDRAM Address[12]
3.3-V LVTTL
DRAM_DQ0
PIN_Y21
SDRAM Data[0]
3.3-V LVTTL
DRAM_DQ1
PIN_Y20
SDRAM Data[1]
3.3-V LVTTL
DRAM_DQ2
PIN_AA22
SDRAM Data[2]
3.3-V LVTTL
DRAM_DQ3
PIN_AA21
SDRAM Data[3]
3.3-V LVTTL
DRAM_DQ4
PIN_Y22
SDRAM Data[4]
3.3-V LVTTL
DRAM_DQ5
PIN_W22
SDRAM Data[5]
3.3-V LVTTL
DRAM_DQ6
PIN_W20
SDRAM Data[6]
3.3-V LVTTL
DRAM_DQ7
PIN_V21
SDRAM Data[7]
3.3-V LVTTL
DRAM_DQ8
PIN_P21
SDRAM Data[8]
3.3-V LVTTL
DRAM_DQ9
PIN_J22
SDRAM Data[9]
3.3-V LVTTL
DRAM_DQ10
PIN_H21
SDRAM Data[10]
3.3-V LVTTL
DRAM_DQ11
PIN_H22
SDRAM Data[11]
3.3-V LVTTL
DRAM_DQ12
PIN_G22
SDRAM Data[12]
3.3-V LVTTL
DRAM_DQ13
PIN_G20
SDRAM Data[13]
3.3-V LVTTL
DRAM_DQ14
PIN_G19
SDRAM Data[14]
3.3-V LVTTL
DRAM_DQ15
PIN_F22
SDRAM Data[15]
3.3-V LVTTL
DRAM_BA0
PIN_T21
SDRAM Bank Address[0]
3.3-V LVTTL
DRAM_BA1
PIN_T22
SDRAM Bank Address[1]
3.3-V LVTTL
DRAM_LDQM
PIN_V22
SDRAM byte Data Mask[0]
3.3-V LVTTL
DRAM_UDQM
PIN_J21
SDRAM byte Data Mask[1]
3.3-V LVTTL
DRAM_RAS_N
PIN_U22
SDRAM Row Address Strobe
3.3-V LVTTL
DRAM_CAS_N
PIN_U21
SDRAM Column Address Strobe
3.3-V LVTTL
DRAM_CKE
PIN_N22
SDRAM Clock Enable
3.3-V LVTTL
DRAM_CLK
PIN_L14
SDRAM Clock
3.3-V LVTTL
DRAM_WE_N
PIN_V20
SDRAM Write Enable
3.3-V LVTTL
DRAM_CS_N
PIN_U20
SDRAM Chip Select
3.3-V LVTTL