Terasic DE10-Lite - Page 55

DE10-Lite
User Manual
54
www.terasic.com
May 11, 2018
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
B
B
a
a
t
t
c
c
h
h
F
F
i
i
l
l
e
e
Demo batch file folder: \SDRAM_RTL_Test\demo_batch
The directory includes the following files:
• Batch file : test.bat
• FPGA configuration file : DE10_LITE_SDRAM_RTL_Test.sof
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
S
S
e
e
t
t
u
u
p
p
• Quartus II v16.0 must be pre-installed to the host PC.
• Connect the DE10-Lite board (J3) to the host PC with a USB cable and install the USB-Blaster
driver if necessary
• Execute the demo batch file “test.bat” from the directory \SDRAM_RTL_Test\demo_batch
• Press KEY0 on the DE10-Lite board to start the verification process. When KEY0 is pressed,
the LEDR [2:0] should turn on. When KEY0 is then released, LEDR1 and LEDR2 should start
blinking.
• After approximately 8 seconds, LEDR1 should stop blinking and stay ON to indicate the test is
PASS. Table 5-1 lists the status of LED indicators.
• If LEDR2 is not blinking, it means 50MHz clock source is not working.
• If LEDR1 failed to remain ON after approximately 8 seconds, the SDRAM test is NG.
• Press KEY0 again to repeat the SDRAM test.
Table 5-1 Status of LED Indicators
Name
Description
LEDR1
ON if the test is PASS after releasing KEY0
LEDR2
Blinks