Texas Instruments AM335x Sitara User Manual

MPU
PLL
PER
PLL
DDR
PLL
CORE
PLL
LCD
PLL
VDDS_PLL_MPU
VDDS_PLL_CORE_LCD
VDDA1P8V_USB0
VDDS_PLL_DDR
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015 www.ti.com
6.1.4 Digital Phase-Locked Loop Power Supply Requirements
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor
of the AM335x device. The AM335x device integrates 5 different DPLLs—Core DPLL, Per DPLL, Display
DPLL, DDR DPLL, MPU DPLL.
Figure 6-8 shows the power supply connectivity implemented in the AM335x device. Table 6-1 provides
the power supply requirements for the DPLL.
Figure 6-8. DPLL Power Supply Connectivity
Table 6-1. DPLL Power Supply Requirements
SUPPLY NAME DESCRIPTION MIN NOM MAX UNIT
VDDA1P8V_USB0 Supply voltage range for USBPHY and PER DPLL, Analog, 1.8 V 1.71 1.8 1.89 V
Max peak-to-peak supply noise 50 mV (p-p)
VDDS_PLL_MPU Supply voltage range for DPLL MPU, analog 1.71 1.8 1.89 V
Max peak-to-peak supply noise 50 mV (p-p)
VDDS_PLL_CORE_LCD Supply voltage range for DPLL CORE and LCD, analog 1.71 1.8 1.89 V
Max peak-to-peak supply noise 50 mV (p-p)
VDDS_PLL_DDR Supply voltage range for DPLL DDR, analog 1.71 1.8 1.89 V
Max peak-to-peak supply noise 50 mV (p-p)
106 Power and Clocking Copyright © 2011–2015, Texas Instruments Incorporated
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Texas Instruments AM335x Sitara Specifications

General

Brand	Texas Instruments
Model	AM335x Sitara
Category	Processor
Language	English