Texas Instruments AM335x Sitara - Page 123

RMII[x]_REFCLK (input)
1
2
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RXER (inputs)
RMII[x]_REFCLK
(Input)
1
2
3
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
www.ti.com SPRS717H –OCTOBER 2011–REVISED MAY 2015
7.6.1.3 EMAC and Switch RMII Electrical Data and Timing
Table 7-13. Timing Requirements for RMII[x]_REFCLK - RMII Mode
(see Figure 7-10)
NO. MIN TYP MAX UNIT
1 t
c(REF_CLK)
Cycle time, REF_CLK 19.999 20.001 ns
2 t
w(REF_CLKH)
Pulse duration, REF_CLK high 7 13 ns
3 t
w(REF_CLKL)
Pulse duration, REF_CLK low 7 13 ns
Figure 7-10. RMII[x]_REFCLK Timing - RMII Mode
Table 7-14. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
(see Figure 7-11)
NO. MIN TYP MAX UNIT
t
su(RXD-REF_CLK)
Setup time, RXD[1:0] valid before REF_CLK
1 t
su(CRS_DV-REF_CLK)
Setup time, CRS_DV valid before REF_CLK 4 ns
t
su(RX_ER-REF_CLK)
Setup time, RX_ER valid before REF_CLK
t
h(REF_CLK-RXD)
Hold time RXD[1:0] valid after REF_CLK
2 t
h(REF_CLK-CRS_DV)
Hold time, CRS_DV valid after REF_CLK 2 ns
t
h(REF_CLK-RX_ER)
Hold time, RX_ER valid after REF_CLK
Figure 7-11. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode
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