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SPRS717H –OCTOBER 2011–REVISED MAY 2015
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7.7.2.3.3.2 Compatible JEDEC DDR3 Devices
Table 7-58 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Table 7-58. Compatible JEDEC DDR3 Devices (Per Interface)
NO. PARAMETER TEST CONDITIONS MIN MAX UNIT
t
C(DDR_CK)
and t
C(DDR_CKn)
DDR3-800
= 3.3 ns
1 JEDEC DDR3 device speed grade
t
C(DDR_CK)
and t
C(DDR_CKn)
DDR3-1600
= 2.5 ns
2 JEDEC DDR3 device bit width x8 x16 bits
3 JEDEC DDR3 device count
(1)
1 2 devices
(1) For valid DDR3 device configurations and device counts, see Section 7.7.2.3.3.1, Figure 7-47, and Figure 7-49.
7.7.2.3.3.3 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 7-59.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 7-59. Minimum PCB Stackup
(1)
LAYER TYPE DESCRIPTION
1 Signal Top signal routing
2 Plane Ground
3 Plane Split Power Plane
4 Signal Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in
the power plane.
176 Peripheral Information and Timings Copyright © 2011–2015, Texas Instruments Incorporated
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