R_SU
(0 to 31)
R_STROBE
(1 to 63)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
14
16
17
15
8
Read Command
LCD_AC_BIAS_EN
(E0)
LCD_MEMORY_CLK
LCD_DATA[15:0]
LCD_VSYNC
(RS)
LCD_HSYNC
(R/ )W
LCD_MEMORY_CLK
(E1)
6
7
6
6
7
6
18
8
9
LCD_AC_BIAS_EN
(E0)
W_SU
(0 to 31)
W_STROBE
(1 to 63)
W_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
LCD_MEMORY_CLK
4
Write Data
5
10
6
LCD_D [15:0]ATA
LCD_VSYNC
(RS)
LCD_HSYNC
(R/ )W
LCD_MEMORY_CLK
(E1)
20
6
7
10
11
6 6
7
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
www.ti.com
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 7-72. Data Write in Hitachi Mode
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
Figure 7-73. Command Read in Hitachi Mode
196 Peripheral Information and Timings Copyright © 2011–2015, Texas Instruments Incorporated
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