AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
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• Five ADPLLs to Generate System Clocks Transmission (SPDIF, IEC60958-1, and
(MPU Subsystem, DDR Interface, USB and AES-3 Formats)
Peripherals [MMC and SD, UART, SPI, I
2
C],
• FIFO Buffers for Transmit and Receive (256
L3, L4, Ethernet, GFX [SGX530], LCD Pixel
Bytes)
Clock)
– Up to Six UARTs
– Power
• All UARTs Support IrDA and CIR Modes
• Two Nonswitchable Power Domains (Real-
• All UARTs Support RTS and CTS Flow
Time Clock [RTC], Wake-Up Logic
Control
[WAKEUP])
• UART1 Supports Full Modem Control
• Three Switchable Power Domains (MPU
– Up to Two Master and Slave McSPI Serial
Subsystem [MPU], SGX530 [GFX],
Interfaces
Peripherals and Infrastructure [PER])
• Up to Two Chip Selects
• Implements SmartReflex™ Class 2B for
• Up to 48 MHz
Core Voltage Scaling Based On Die
– Up to Three MMC, SD, SDIO Ports
Temperature, Process Variation, and
• 1-, 4- and 8-Bit MMC, SD, SDIO Modes
Performance (Adaptive Voltage Scaling
[AVS])
• MMCSD0 has Dedicated Power Rail for
1.8‑V or 3.3-V Operation
• Dynamic Voltage Frequency Scaling (DVFS)
• Up to 48-MHz Data Transfer Rate
• Real-Time Clock (RTC)
• Supports Card Detect and Write Protect
– Real-Time Date (Day-Month-Year-Day of Week)
and Time (Hours-Minutes-Seconds) Information
• Complies With MMC4.3, SD, SDIO 2.0
Specifications
– Internal 32.768-kHz Oscillator, RTC Logic and
1.1-V Internal LDO
– Up to Three I
2
C Master and Slave Interfaces
– Independent Power-on-Reset
• Standard Mode (up to 100 kHz)
(RTC_PWRONRSTn) Input
• Fast Mode (up to 400 kHz)
– Dedicated Input Pin (EXT_WAKEUP) for
– Up to Four Banks of General-Purpose I/O
External Wake Events
(GPIO) Pins
– Programmable Alarm Can be Used to Generate
• 32 GPIO Pins per Bank (Multiplexed With
Internal Interrupts to the PRCM (for Wakeup) or
Other Functional Pins)
Cortex-A8 (for Event Notification)
• GPIO Pins Can be Used as Interrupt Inputs
– Programmable Alarm Can be Used With
(up to Two Interrupt Inputs per Bank)
External Output (PMIC_POWER_EN) to Enable
– Up to Three External DMA Event Inputs that can
the Power Management IC to Restore Non-RTC
Also be Used as Interrupt Inputs
Power Domains
– Eight 32-Bit General-Purpose Timers
• Peripherals
• DMTIMER1 is a 1-ms Timer Used for
– Up to Two USB 2.0 High-Speed OTG Ports
Operating System (OS) Ticks
With Integrated PHY
• DMTIMER4–DMTIMER7 are Pinned Out
– Up to Two Industrial Gigabit Ethernet MACs (10,
– One Watchdog Timer
100, 1000 Mbps)
– SGX530 3D Graphics Engine
• Integrated Switch
• Tile-Based Architecture Delivering up to 20
• Each MAC Supports MII, RMII, RGMII, and
Million Polygons per Second
MDIO Interfaces
• Universal Scalable Shader Engine (USSE) is
• Ethernet MACs and Switch Can Operate
a Multithreaded Engine Incorporating Pixel
Independent of Other Functions
and Vertex Shader Functionality
• IEEE 1588v2 Precision Time Protocol (PTP)
• Advanced Shader Feature Set in Excess of
– Up to Two Controller-Area Network (CAN) Ports
Microsoft VS3.0, PS3.0, and OGL2.0
• Supports CAN Version 2 Parts A and B
• Industry Standard API Support of Direct3D
– Up to Two Multichannel Audio Serial Ports
Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0,
(McASPs)
and OpenMax
• Transmit and Receive Clocks up to 50 MHz
• Fine-Grained Task Switching, Load
• Up to Four Serial Data Pins per McASP Port
Balancing, and Power Management
With Independent TX and RX Clocks
• Advanced Geometry DMA-Driven Operation
• Supports Time Division Multiplexing (TDM),
for Minimum CPU Interaction
Inter-IC Sound (I2S), and Similar Formats
• Programmable High-Quality Image Anti-
• Supports Digital Audio Interface
Aliasing
2 Device Overview Copyright © 2011–2015, Texas Instruments Incorporated
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