Texas Instruments AM335x Sitara User Manual

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
AM335x Sitara™ Processors
1 Device Overview
1.1 Features
1
– Supports Protocols such as EtherCAT
®
,
• Up to 1-GHz Sitara™ ARM
®
Cortex
®
-A8 32‑Bit
PROFIBUS, PROFINET, EtherNet/IP™, and
RISC Processor
More
– NEON™ SIMD Coprocessor
– Two Programmable Real-Time Units (PRUs)
– 32KB of L1 Instruction and 32KB of Data Cache
• 32-Bit Load/Store RISC Processor Capable
With Single-Error Detection (Parity)
of Running at 200 MHz
– 256KB of L2 Cache With Error Correcting Code
• 8KB of Instruction RAM With Single-Error
(ECC)
Detection (Parity)
– 176KB of On-Chip Boot ROM
• 8KB of Data RAM With Single-Error
– 64KB of Dedicated RAM
Detection (Parity)
– Emulation and Debug - JTAG
• Single-Cycle 32-Bit Multiplier With 64-Bit
– Interrupt Controller (up to 128 Interrupt
Accumulator
Requests)
• Enhanced GPIO Module Provides Shift-
• On-Chip Memory (Shared L3 RAM)
In/Out Support and Parallel Latch on
– 64KB of General-Purpose On-Chip Memory
External Signal
Controller (OCMC) RAM
– 12KB of Shared RAM With Single-Error
– Accessible to All Masters
Detection (Parity)
– Supports Retention for Fast Wakeup
– Three 120-Byte Register Banks Accessible by
• External Memory Interfaces (EMIF)
Each PRU
– mDDR(LPDDR), DDR2, DDR3, DDR3L
– Interrupt Controller Module (INTC) for Handling
Controller:
System Input Events
• mDDR: 200-MHz Clock (400-MHz Data
– Local Interconnect Bus for Connecting Internal
Rate)
and External Masters to the Resources Inside
• DDR2: 266-MHz Clock (532-MHz Data Rate)
the PRU-ICSS
• DDR3: 400-MHz Clock (800-MHz Data Rate)
– Peripherals Inside the PRU-ICSS:
• DDR3L: 400-MHz Clock (800-MHz Data
• One UART Port With Flow Control Pins,
Rate)
Supports up to 12 Mbps
• 16-Bit Data Bus
• One Enhanced Capture (eCAP) Module
• 1GB of Total Addressable Space
• Two MII Ethernet Ports that Support
Industrial Ethernet, such as EtherCAT
• Supports One x16 or Two x8 Memory Device
Configurations
• One MDIO Port
– General-Purpose Memory Controller (GPMC)
• Power, Reset, and Clock Management (PRCM)
Module
• Flexible 8-Bit and 16-Bit Asynchronous
Memory Interface With up to Seven Chip
– Controls the Entry and Exit of Stand-By and
Selects (NAND, NOR, Muxed-NOR, SRAM)
Deep-Sleep Modes
• Uses BCH Code to Support 4-, 8-, or 16-Bit
– Responsible for Sleep Sequencing, Power
ECC
Domain Switch-Off Sequencing, Wake-Up
Sequencing, and Power Domain Switch-On
• Uses Hamming Code to Support 1-Bit ECC
Sequencing
– Error Locator Module (ELM)
– Clocks
• Used in Conjunction With the GPMC to
• Integrated 15- to 35-MHz High-Frequency
Locate Addresses of Data Errors from
Oscillator Used to Generate a Reference
Syndrome Polynomials Generated Using a
Clock for Various System and Peripheral
BCH Algorithm
Clocks
• Supports 4-, 8-, and 16-Bit per 512-Byte
• Supports Individual Clock Enable and
Block Error Location Based on BCH
Disable Control for Subsystems and
Algorithms
Peripherals to Facilitate Reduced Power
• Programmable Real-Time Unit Subsystem and
Consumption
Industrial Communication Subsystem (PRU-ICSS)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Texas Instruments AM335x Sitara Specifications

General

Architecture	ARM Cortex-A8
Core Count	1
Clock Speed	Up to 1 GHz
Process Technology	45 nm
Integrated Graphics	SGX530
Memory Support	DDR2, DDR3, DDR3L
Interfaces	UART, I2C, CAN, USB, Ethernet
Integrated Peripherals	ADC, PWM, Timers, Watchdog Timer
Package / Case	BGA
USB	USB 2.0
Ethernet	10/100 Ethernet MAC
UART	6x UART
I2C	3x I2C
ADC	8-channel 12-bit ADC
Watchdog Timer	1x 32-bit Watchdog Timer
Operating Temperature	-40°C to 105°C
Power Supply	1.1V to 1.3V (Core), 1.8V to 3.3V (I/O)

Summary

Device Overview

Features

Lists the key hardware capabilities and interfaces of the AM335x processors.

Description

Functional Block Diagram

Revision History

Device Comparison

Terminal Configuration and Functions

Pin Diagrams

Shows the physical pin assignments for the ZCE and ZCZ packages.

Pin Attributes

Details pin characteristics, signal names, and multiplexing modes.

Signal Descriptions

Explains the signals and their potential multiplexing configurations.

Peripheral Information and Timings

Parameter Information

Provides general information on timing parameters and their relation to operating conditions.

Recommended Clock and Control Signal Transition Behavior

Guidelines for monotonic transitions of clock and control signals.

Controller Area Network (CAN)

DCAN Electrical Data and Timing

Electrical data and timing specifications for the DCAN interface.

DMTimer

DMTimer Electrical Data and Timing

Electrical data and timing requirements for the DMTimer peripheral.

Ethernet Media Access Controller (EMAC) and Switch

EMAC and Switch Electrical Data and Timing

Electrical and timing specifications for the EMAC and Switch.

External Memory Interfaces

General-Purpose Memory Controller (GPMC)

Detailed information on the General-Purpose Memory Controller (GPMC).

GPMC and NOR Flash—Synchronous Mode

Timing conditions for GPMC in synchronous mode with NOR flash.

GPMC and NOR Flash—Asynchronous Mode

Timing conditions for GPMC in asynchronous mode with NOR flash.

mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface

Describes interfaces for various DDR memory types.

DDR2 Routing Guidelines

Routing guidelines specific to the DDR2 interface.

PCB Stackup

Minimum PCB stackup requirements for DDR2 routing.

Placement

Placement guidelines for DDR2 devices relative to the AM335x.

Bulk Bypass Capacitors

Recommendations for bulk bypass capacitors for DDR2.

Net Classes

Definition of net classes for DDR2 interface signals.

DDR2 Signal Termination

Specifications for DDR2 signal termination.

DDR3 and DDR3L Routing Guidelines

Routing guidelines for DDR3 and DDR3L memory interfaces.

PCB Stackup

Minimum PCB stackup requirements for DDR3 routing.

Placement

Placement guidelines for DDR3 devices relative to the AM335x.

DDR3 Keepout Region

Definition of the keepout region for DDR3 circuitry.

Bulk Bypass Capacitors

Recommendations for bulk bypass capacitors for DDR3.

High-Speed Bypass Capacitors

Specifications for high-speed bypass capacitors for DDR3.

Net Classes

Definition of net classes for DDR3 interface signals.

DDR3 Signal Termination

Specifications for DDR3 signal termination.

DDR_VREF Routing

Guidelines for routing the DDR_VREF signal.

VTT

Details on the VTT supply and its routing.

CK and ADDR_CTRL Topologies, Two DDR3 Devices

Topologies for CK net classes with two DDR3 devices.

CK and ADDR_CTRL Routing, Two DDR3 Devices

Routing guidelines for CK and ADDR_CTRL with two DDR3 devices.

CK and ADDR_CTRL Topologies, One DDR3 Device

Topologies for CK net classes with one DDR3 device.

CK and ADDR_CTRL Routing, One DDR3 Device

Routing guidelines for CK and ADDR_CTRL with one DDR3 device.

Data Topologies and Routing Definition

Defines data line topologies and routing.

DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices

Topologies for DQS[x] and DQ[x] signals.

CK and ADDR_CTRL Routing Specification

Specifications for CK and ADDR_CTRL routing.

DQS[x] and DQ[x] Routing Specification

Specifications for DQS[x] and DQ[x] routing.

I2C

I2C Electrical Data and Timing

Electrical data and timing for the I2C interface.

JTAG Electrical Data and Timing

LCD Controller (LCDC)

LCD Interface Display Driver (LIDD Mode)

Details regarding the LCD Interface Display Driver (LIDD) mode.

LCD Raster Mode

Switching characteristics for LCD raster mode operation.

Multichannel Audio Serial Port (McASP)

McASP Device-Specific Information

Device-specific information for the McASP peripheral.

McASP Electrical Data and Timing

Electrical data and timing for the McASP interface.

Multichannel Serial Port Interface (McSPI)

McSPI Electrical Data and Timing

Electrical data and timing for the McSPI interface.

McSPI—Slave Mode

Timing requirements for McSPI in slave mode.

McSPI—Master Mode

Timing requirements for McSPI in master mode.

Multimedia Card (MMC) Interface

MMC Electrical Data and Timing

Electrical data and timing for the MMC interface.

Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)

Programmable Real-Time Unit (PRU-ICSS PRU)

Details on the PRU-ICSS PRU module.

PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing

Electrical data and timing for PRU-ICSS PRU in I/O mode.

PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing

Electrical data and timing for PRU-ICSS PRU Parallel Capture mode.

PRU-ICSS PRU Shift Mode Electrical Data and Timing

Electrical data and timing for PRU-ICSS PRU Shift Mode.

Universal Asynchronous Receiver Transmitter (UART)

UART Electrical Data and Timing

Electrical data and timing for the UART interface.

UART IrDA Interface

Details on the UART IrDA interface parameters.

Device and Documentation Support

Device Support

Information on device support and development tools.

Development Support

Overview of software and hardware development tools.

Documentation Support

Links to relevant technical documentation and resources.

Related Documentation

Lists key documents describing the AM335x MPU and peripherals.

Community Resources

Links to TI community resources for support and collaboration.

Trademarks

Lists trademarks relevant to the AM335x platform and TI products.

Electrostatic Discharge Caution

Important warnings and precautions regarding ESD handling.

Mechanical, Packaging, and Orderable Information

Via Channel

Details the Via Channel technology used in ZCZ packages.

Packaging Information

Provides information on mechanical packaging and orderable parts.