Texas Instruments AM335x Sitara User Manual

A1 A2
AM335x
Address and Control
Output Buffer
DDR3 Address and Control Input Buffers
A3
AT
Vtt
Address and Control
Terminator
Rtt
AS AS
AS-
AS+
A1 A2
AM335x
Differential Clock
Output Buffer
DDR3 Differential CK Input Buffers
Routed as Differential Pair
A3
AT
Rcp
Clock Parallel
Terminator
A1 A2
A3
AT
AS-
AS+
Rcp
Cac
VDDS_DDR
0.1 µF
+
–
+
–
+
–
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015 www.ti.com
7.7.2.3.4.1 Two DDR3 Devices
Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as
one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a
pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 7-52 shows the topology of the CK net classes and Figure 7-53 shows the topology for the
corresponding ADDR_CTRL net classes.
Figure 7-52. CK Topology for Two DDR3 Devices
Figure 7-53. ADDR_CTRL Topology for Two DDR3 Devices
7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
Figure 7-54 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 7-55
shows the corresponding ADDR_CTRL routing.
182 Peripheral Information and Timings Copyright © 2011–2015, Texas Instruments Incorporated
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Texas Instruments AM335x Sitara Specifications

General

Brand	Texas Instruments
Model	AM335x Sitara
Category	Processor
Language	English