AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
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7.7.2.2.2.7 High-Speed (HS) Bypass Capacitors
HS bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to
minimize the parasitic series inductance of the HS bypass capacitors, AM335x device DDR2 power, and
AM335x device DDR2 ground connections. Table 7-49 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB.
Table 7-49. HS Bypass Capacitors
NO. PARAMETER MIN MAX UNIT
1 HS bypass capacitor package size
(1)
0402 10 mils
2 Distance from HS bypass capacitor to device being bypassed 250 mils
3 Number of connection vias for each HS bypass capacitor
(2)
2 vias
4 Trace length from bypass capacitor contact to connection via 30 mils
5 Number of connection vias for each AM335x VDDS_DDR and VSS terminal 1 vias
6 Trace length from AM335x VDDS_DDR and VSS terminal to connection via 35 mils
7 Number of connection vias for each DDR2 device power and ground terminal 1 vias
8 Trace length from DDR2 device power and ground terminal to connection via 35 mils
9 AM335x VDDS_DDR HS bypass capacitor count
(3)
10 devices
10 AM335x VDDS_DDR HS bypass capacitor total capacitance 0.6 μF
11 DDR2 device HS bypass capacitor count
(3)(4)
8 devices
12 DDR2 device HS bypass capacitor total capacitance
(4)
0.4 μF
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Per DDR2 device.
7.7.2.2.2.8 Net Classes
Table 7-50 lists the clock net classes for the DDR2 interface. Table 7-51 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 7-50. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK DDR_CK and DDR_CKn
DQS0 DDR_DQS0 and DDR_DQSn0
DQS1 DDR_DQS1 and DDR_DQSn1
Table 7-51. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS AM335x PIN NAMES
NET CLASS
ADDR_CTRL CK DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE, DDR_ODT
DQ0 DQS0 DDR_D[7:0], DDR_DQM0
DQ1 DQS1 DDR_D[15:8], DDR_DQM1
166 Peripheral Information and Timings Copyright © 2011–2015, Texas Instruments Incorporated
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