AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
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7.12.1.2 McSPI—Master Mode
Table 7-83. McSPI Timing Conditions – Master Mode
LOW LOAD HIGH LOAD
PARAMETER UNIT
MIN MAX MIN MAX
Input Conditions
t
r
Input signal rise time 8 8 ns
t
f
Input signal fall time 8 8 ns
Output Condition
C
load
Output load capacitance 5 25 pF
Table 7-84. Timing Requirements for McSPI Input Timings – Master Mode
(see Figure 7-90)
OPP100 OPP50
NO. LOW LOAD HIGH LOAD LOW LOAD HIGH LOAD UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
t
su(SOMI-
Setup time, SPI_D[x] (SOMI) valid before
4 2.29 3.02 2.29 3.02 ns
SPICLKH)
SPI_CLK active edge
(1)
Industrial extended
temperature 7.1 7.1 7.1 7.1
Hold time, SPI_D[x]
t
h(SPICLKH-
(-40°C to 125°C)
5 (SOMI) valid after ns
SOMI)
SPI_CLK active edge
(1)
All other
4.7 4.7 4.7 4.7
temperature ranges
(1) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 7-85. Switching Characteristics for McSPI Output Timings – Master Mode
(see Figure 7-91)
OPP100 OPP50
NO. PARAMETER LOW LOAD HIGH LOAD LOW LOAD HIGH LOAD UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 t
c(SPICLK)
Cycle time, SPI_CLK 20.8 20.8 41.6 41.6 ns
Typical pulse duration, 0.5P – 0.5P + 0.5P – 0.5P + 0.5P – 0.5P + 0.5P – 0.5P +
2 t
w(SPICLKL)
ns
SPI_CLK low 1.04
(1)
1.04
(1)
2.08
(1)
2.08
(1)
1.04
(1)
1.04
(1)
2.08
(1)
2.08
(1)
Typical pulse duration, 0.5P – 0.5P + 0.5P – 0.5P + 0.5P – 0.5P + 0.5P – 0.5P +
t
w(SPICLKH)
ns
SPI_CLK high 1.04
(1)
1.04
(1)
2.08
(1)
2.08
(1)
1.04
(1)
1.04
(1)
2.08
(1)
2.08
(1)
3
t
r(SPICLK)
Rising time, SPI_CLK 3.82 3.82 3.82 3.82 ns
t
f(SPICLK)
Falling time, SPI_CLK 3.44 3.44 3.44 3.44 ns
Delay time, SPI_CLK
6 t
d(SPICLK-SIMO)
active edge to SPI_D[x] –3.57 3.57 –4.62 4.62 –3.57 3.57 –4.62 4.62 ns
(SIMO) transition
(2)
Delay time, SPI_CS active
7 t
d(CS-SIMO)
edge to SPI_D[x] (SIMO) 3.57 4.62 3.57 4.62 ns
transition
(2)
Mode 1
Delay time,
A – 4.2
(4)
A – 2.54
(4)
A – 4.2
(4)
A – 2.54
(4)
ns
and 3
(3)
SPI_CS active
8 t
d(CS-SPICLK)
to SPI_CLK
Mode 0
B – 4.2
(5)
B – 2.54
(5)
B – 4.2
(5)
B – 2.54
(5)
ns
first edge
and 2
(3)
Delay time, Mode 1
B – 4.2
(5)
B – 2.54
(5)
B – 4.2
(5)
B – 2.54
(5)
ns
SPI_CLK last and 3
(3)
9 t
d(SPICLK-CS)
edge to
Mode 0
SPI_CS
A – 4.2
(4)
A – 2.54
(4)
A – 4.2
(4)
A – 2.54
(4)
ns
and 2
(3)
inactive
(1) P = SPI_CLK period.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
218 Peripheral Information and Timings Copyright © 2011–2015, Texas Instruments Incorporated
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