LCD_D [15:0]ATA
LCD_AC_BIAS_EN
(CS0)
LCD_VSYNC
(ALE)
LCD_HSYNC
(WS)
LCD_MEMORY_CLK
(MCLK) Sync Mode
LCD_PCLK
(RS)
W_SU
(0−31)
W_STROBE
(1−63)
W_HOLD
(1−15)
CS_DELAY
(0−3)
Write Address
Read
Data
LCD_MEMORY_CLK
(CS1) Async Mode
6 6 6
19
4
20
6
8
10
6 6
8
10
77
12 12
6
5 14
15
6
R_SU
(0−31)
R_STROBE
(1−63)
CS_DELAY
(0−3)
R_HOLD
(1−15)
16
18
17
1
3
2
9
11
13
7
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
www.ti.com
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 7-79. Micro-Interface Graphic Display Intel Read
202 Peripheral Information and Timings Copyright © 2011–2015, Texas Instruments Incorporated
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