LCD_D [15:0]ATA
LCD_AC_BIAS_EN
(CS0)
LCD_VSYNC
(ALE)
LCD_HSYNC
(WS)
LCD_MEMORY_CLK
(MCLK) Sync Mode
LCD_PCLK
(RS)
Read
Status
LCD_MEMORY_CLK
(CS1) Async Mode
6
6
12 12
6
14
15
6
R_SU
(0−31)
R_STROBE
(1−63)
CS_DELAY
(0−3)
R_HOLD
(1−15)
16
18
17
8 8
13
9
7
1
3
2
19
7
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
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SPRS717H –OCTOBER 2011–REVISED MAY 2015
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 7-80. Micro-Interface Graphic Display Intel Status
Copyright © 2011–2015, Texas Instruments Incorporated Peripheral Information and Timings 203
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