LCD_HSYNC
LCD_VSYNC
(1 to 2048)
Frame Time
LPP_B10 + LPP
LCD_D [7:0]ATA
1, L−2
P, L−2
1, L−4
P, L−4
Line
Time
LCD_HSYNC
10 10
LCD_PCLK
LCD_D [7:0]ATA
1, 5 2, 6 P, 6
P, 5
2, 5
1, 6
PPLMSB + PPLLSB
16 x (1 to 2048)
HBP
(1 to 256)
Line 5
HFP
(1 to 64)
HSW PPLMSB + PPLLSB
16 x (1 to 2048)
Line 6
1, 1:
P, 1
1, 5:
P, 5
1, L−1
P, L−1
1, L
1, L−1
P, L−1
1, L−3
P, L−3
VBP = 0
VFP = 0
VSW = 1
Data
LCD_AC_BIAS_EN
ACB
(0 to 255)
ACB
(0 to 255)
1, 4:
P, 4
1, 3:
P, 3
1, 2:
P, 2
1, L:
P, L
1, 6:
P, 6
1, 2
P, 2
1, 1
P, 1
1, L
P, L
(1 to 256)
11
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
www.ti.com
SPRS717H –OCTOBER 2011–REVISED MAY 2015
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 7-83. LCD Raster-Mode Passive
Copyright © 2011–2015, Texas Instruments Incorporated Peripheral Information and Timings 207
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352