AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
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Table 5-11 summarizes the power consumption of the AM335x low-power modes.
Table 5-11. AM335x Low-Power Modes Power Consumption Summary
POWER POWER DOMAINS, CLOCKS, AND
APPLICATION STATE NOM MAX UNIT
MODES VOLTAGE SUPPLY STATES
Power supplies:
• All power supplies are ON.
• VDD_MPU = 0.95 V (nom)
DDR memory is in self-refresh and
• VDD_CORE = 0.95 V (nom)
contents are preserved. Wake up
Clocks:
from any GPIO. Cortex-A8
• Main Oscillator (OSC0) = ON
context/register contents are lost
Standby and must be saved before entering 16.5 22.0 mW
• All DPLLs are in bypass.
standby. On exit, context must be
Power domains:
restored from DDR. For wake-up,
• PD_PER = ON
boot ROM executes and branches
• PD_MPU = OFF
to system resume.
• PD_GFX = OFF
• PD_WKUP = ON
DDR is in self-refresh.
Power supplies:
• All power supplies are ON.
• VDD_MPU = 0.95 V (nom)
On-chip peripheral registers are
• VDD_CORE = 0.95 V (nom)
preserved. Cortex-A8
Clocks:
context/registers are lost, so the
• Main Oscillator (OSC0) = OFF
application needs to save them to
Deepsleep1 the L3 OCMC RAM or DDR before 6.0 10.0 mW
• All DPLLs are in bypass.
entering DeepSleep. DDR is in self-
Power domains:
refresh. For wake-up, boot ROM
• PD_PER = ON
executes and branches to system
• PD_MPU = OFF
resume.
• PD_GFX = OFF
• PD_WKUP = ON
DDR is in self-refresh.
Power supplies:
• All power supplies are ON.
PD_PER peripheral and Cortex-
• VDD_MPU = 0.95 V (nom)
A8/MPU register information will be
• VDD_CORE = 0.95 V (nom)
lost. On- chip peripheral register
Clocks:
(context) information of PD-PER
• Main Oscillator (OSC0) = OFF
domain needs to be saved by
Deepsleep0 application to SDRAM before 3.0 4.3 mW
• All DPLLs are in bypass.
entering this mode. DDR is in self-
Power domains:
refresh. For wake-up, boot ROM
• PD_PER = OFF
executes and branches to
• PD_MPU = OFF
peripheral context restore followed
• PD_GFX = OFF
by system resume.
• PD_WKUP = ON
DDR is in self-refresh.
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