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Texas Instruments MSPM0G3507 User Manual

Texas Instruments MSPM0G3507
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8 Detailed Description
The following sections describe all of the components that make up the devices in this data sheet. The
peripherals integrated into these devices are configured by software through Memory Mapped Registers
(MMRs). For more details, see the corresponding chapter of the MSPM0 G-Series 80-MHz Microcontrollers
Technical Reference Manual.
8.1 CPU
The CPU sub system (MCPUSS) implements an ARM Cortex-M0+ CPU, an instruction pre-fetch/cache, a
system timer, a memory protection unit, and interrupt management features. The ARM Cortex-M0+ is a cost-
optimized, 32-bit CPU which delivers high performance and low power to embedded applications. Key features
of the CPU Sub System include:
ARM Cortex-M0+ CPU supporting clock frequencies from 32kHz to 80MHz
ARMv6-M Thumb instruction set (little endian) with single-cycle 32x32 multiply instruction
Single-cycle access to GPIO registers via ARM single-cycle IO port
Pre-fetch logic to improve sequential code execution, and I-cache with 4 64-bit cache lines
System timer (SysTick) with 24-bit down counter and automatic reload
Memory protection unit (MPU) with 8 programmable regions
Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail-chaining
Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency
8.2 Operating Modes
MSPM0G MCUs provide five main operating modes (power modes) to allow for optimization of the device power
consumption based on application requirements. In order of decreasing power, the modes are: RUN, SLEEP,
STOP, STANDBY, and SHUTDOWN. The CPU is active executing code in RUN mode. Peripheral interrupt
events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN mode
completely disables the internal core regulator to minimize power consumption, and wake is only possible via
NRST, SWD, or a logic level match on certain IOs. RUN, SLEEP, STOP, and STANDBY modes also include
several configurable policy options (e.g. RUN.x) for balancing performance with power consumption.
To further balance performance and power consumption, MSPM0G devices implement two power domains: PD1
(for the CPU, memories, and high performance peripherals), and PD0 (for low speed, low power peripherals).
PD1 is always powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 is always powered in
RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both disabled in SHUTDOWN mode.
8.2.1 Functionality by Operating Mode (MSPM0G350x)
Supported functionality in each operating mode is given in Table 8-1.
Functional key:
EN: The function is enabled in the specified mode.
DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's
configuration is retained.
OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.
NS: The function is not automatically disabled in the specified mode, but it is not supported.
OFF: The function is fully powered off in the specified mode, and no configuration information is retained.
When waking up from an OFF state, all module registers must be re-configured to the desired settings by
application software.
MSPM0G3507, MSPM0G3506, MSPM0G3505
SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
www.ti.com
ADVANCE INFORMATION
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: MSPM0G3507 MSPM0G3506 MSPM0G3505

Questions and Answers:

Texas Instruments MSPM0G3507 Specifications

General IconGeneral
Microcontroller SeriesMSPM0
CoreArm Cortex-M0+
Flash Memory128 KB
Max Clock Frequency80 MHz
Communication InterfacesUART, SPI, I2C
Package TypeLQFP
Operating Voltage1.62 V to 3.63 V

Summary

1 Features

Core and Operating Characteristics

Details on the CPU core, frequency, and operating voltage/temperature range.

Memory and Analog Peripherals

Information on flash/SRAM, ADCs, DAC, op-amps, and amplifiers.

Digital and System Features

Covers timers, communication interfaces, clock system, and security features.

Support and Package Information

Includes development tools, package types, and family member variants.

2 Applications

3 Description

4 Functional Block Diagram

5 Device Comparison

6 Pin Configuration and Functions

6.1 Pin Diagrams

Visual representations of pin assignments for different package types.

6.2 Pin Attributes

Table describing the function and availability of each pin across packages.

6.3 Signal Descriptions

Detailed descriptions of all available peripheral signals and their pin mappings.

6.4 Connections for Unused Pins

Guidance on proper termination for unused device pins.

7 Specifications

7.1 Absolute Maximum Ratings

Defines the stress limits beyond which device damage may occur.

7.2 ESD Ratings

Specifies electrostatic discharge protection levels for device handling.

7.3 Recommended Operating Conditions

Defines the voltage, temperature, and frequency ranges for reliable operation.

7.4 Thermal Information

7.5 Supply Current Characteristics

7.5.1 RUN/SLEEP Modes

Supply current data for RUN and SLEEP modes at different MCLK frequencies.

7.5.2 STOP/STANDBY Modes

Supply current data for STOP and STANDBY modes at different ULPCLK frequencies.

7.6 Power Supply Sequencing

7.6.1 POR and BOR

Details on POR and BOR voltage levels, hysteresis, and delay parameters.

7.7 Flash Memory Characteristics

7.8 Timing Characteristics

7.9 Clock Specifications

7.9.1 System Oscillator (SYSOSC)

Parameters and accuracy for the internal system oscillator.

7.9.2 Low Frequency Oscillator (LFOSC)

Specifications for the low-frequency internal oscillator.

7.9.3 System Phase Lock Loop (SYSPLL)

Characteristics of the phase-locked loop for frequency synthesis.

7.9.5 High Frequency Crystal/Clock

7.10 Digital IO

7.10.1 Electrical Characteristics

Defines voltage levels, hysteresis, and leakage for digital I/O.

7.10.2 Switching Characteristics

Specifies output frequency and rise/fall times for digital I/O.

7.11 Analog Mux VBOOST

7.12 ADC

7.12.1 Electrical Characteristics

Defines ADC input voltage, resolution, current, and reference parameters.

7.13 Temperature Sensor

7.14 VREF

7.14.1 Voltage Characterisitcs

Details minimum supply voltage and output voltage characteristics for VREF.

7.15 Comparator (COMP)

7.15.1 Comparator Electrical Characteristics

Defines input range, hysteresis, delay, and current for comparators.

7.16 DAC

7.16.1 DAC_Supply Specifications

Specifies voltage and current requirements for the DAC.

7.17 GPAMP

7.17.1 Electrical Characteristics

Defines common mode range, gain, noise, and slew rate for GPAMP.

7.17.2 Switching Characteristics

Specifies enable, disable, and settling times for the GPAMP.

7.18 OPA

7.18.1 Electrical Characteristics

Defines common mode range, quiescent current, and noise for OPAs.

7.18.2 Switching Characteristics

Specifies enable, disable, and settling times for the OPAs.

7.18.3 PGA Mode

Provides gain characteristics and resistance values for the programmable gain amplifier.

7.19 I2C

7.19.1 I2C Characteristics

Defines clock frequency, hold times, and setup times for I2C communication.

7.19.2 I2C Filter

Specifies parameters for the input filter used to suppress spikes in I2C signals.

7.20 SPI

7.20.1 SPI

Defines SPI clock frequency, duty cycle, and data timing parameters.

7.20.2 SPI Timing Diagram

Illustrates timing for SPI communication in controller mode.

7.21 UART

7.22 TIMx

7.23 TRNG

7.23.1 TRNG Electrical Characteristics

Specifies current consumption for the TRNG module.

7.24 Emulation and Debug

7.24.1 SWD Timing

Defines the clock frequency for the SWD debug interface.

8 Detailed Description

8.1 CPU

Describes the ARM Cortex-M0+ CPU core, its features, and sub-systems.

8.2 Operating Modes

Explains the five device operating modes for power optimization.

8.3 Power Management Unit (PMU)

Details the PMU's role in supply monitoring and power management.

8.5 DMA

8.7 Memory

8.7.1 Memory Organization

Details the address ranges for code, SRAM, and peripheral memory regions.

8.10 GPIO

8.12 ADC

8.15 COMP

8.16 DAC

8.24 I2C

8.25 SPI

8.32 Serial Wire Debug Interface

8.33 Boot Strap Loader (BSL)

8.35 Identification

9 Applications, Implementation, and Layout

9.1 Typical Application

Shows a basic application schematic with recommended external components.

10 Device and Documentation Support

10.1 Getting Started and Next Steps

Guides for beginning development with MSPM0 MCUs.

10.2 Device Nomenclature

Explains the naming convention used for MSP MCU devices.

10.3 Tools and Software

Lists available development tools, IDEs, and software kits.

10.4 Documentation Support

10.5 Support Resources

10.7 Electrostatic Discharge Caution

11 Mechanical, Packaging, and Orderable Information

12 Revision History

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