8.24 I2C
The inter-integrated circuit interface (I
2
C) peripherals in these devices provide bidirectional data transfer with
other I2C devices on the bus and support the following key features:
• 7-bit and 10-bit addressing mode with multiple 7-bit target addresses
• Multiple-controller transmitter or receiver mode
• Target receiver or transmitter mode with configurable clock stretching
• Support Standard-mode (Sm), with a bit rate up to 100 kbit/s
• Support Fast-mode (Fm), with a bit rate up to 400 kbit/s
• Support Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s
– Supported on open drain IOs (ODIO) and high-drive (HDIO) IOs only
• Separated transmit and receive FIFOs support DMA data transfer
• Support SMBus 3.0 with PEC, ARP, timeout detection and host support
• Wakeup from low power mode on address match
• Support analog and digital glitch filter for input signal glitch suppression
• 8-entry transmit and receive FIFOs
For more details, see the I2C chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Manual.
8.25 SPI
The serial peripheral interface (SPI) peripherals in these devices support the following key features:
• Support ULPCLK/2 bit rate and up to 32Mbits/s in both controller and peripheral mode
1
• Configurable as a controller or a peripheral
• Configurable chip select for both controller and peripheral
• Programmable clock prescaler and bit rate
• Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode)
• Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU
performance
• Transmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transfer
• Supports TI mode, Motorola mode and National Microwire format
For more details, see the SPI chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Manual.
8.26 CAN-FD
The controller area network (CAN) controller enables communication with a CAN2.0A, CAN2.0B, or CAN-FD bus
and is compliant to ISO 11898-1:2015 standard supporting upto 5Mbit/s bit rate. Key features of the CAN-FD
peripheral include:
• Full support for 64-byte CAN-FD frames
• Dedicated 1kB message SRAM with ECC
• Configurable transmit FIFO, transmit queue and event FIFO (up to 32 elements)
• Up to 32 dedicated transmit buffers and 64 dedicated receive buffers
• Two configurable receive FIFOs (up to 64 elements each)
• Up to 128 filter elements
• Two interrupt lines
• Power-down and wake-up support
• Timestamp counter
For more details, see the CAN-FD chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical
Reference Manual.
1
Only SPI signals on HSIO pins support data rate > 16 Mbits/s; see the Pin Diagrams section for HSIO pins.
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MSPM0G3507, MSPM0G3506, MSPM0G3505
SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
Copyright © 2023 Texas Instruments Incorporated
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