7.19.3 I
2
C Timing Diagram
SDA
SCL
t
SU,DAT
t
HD,STA
t
HD,STA
t
VD,DAT
t
SU,STO
t
BUF
t
SU,STA
t
SP
tt
HIGH
t
tt
LOW
t
t
HD,DAT
Figure 7-5. I2C Timing Diagram
7.20 SPI
7.20.1 SPI
over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
SPI
f
SPI
SPI clock frequency
Clock max speed = 32MHz
1.62 < VDD < 3.6V
Controller mode
16 MHz
f
SPI
SPI clock frequency
Clock max speed = 32MHz
1.62 < VDD < 3.6V
Peripheral mode
16 MHz
f
SPI
SPI clock frequency
Clock max speed >= 32MHz
1.62 < VDD < 3.6V
Controller mode
16 MHz
f
SPI
SPI clock frequency
Clock max speed >= 48MHz
1.62 < VDD < 2.7V
Controller mode with High speed IO
24 MHz
f
SPI
SPI clock frequency
Clock max speed >= 64MHz
2.7 < VDD < 3.6V
Controller mode with High speed IO
32 MHz
f
SPI
SPI clock frequency
Clock max speed >= 32MHz
1.62 < VDD < 3.6V
Peripheral mode
16 MHz
f
SPI
SPI clock frequency
Clock max speed >= 48MHz
1.62 < VDD < 2.7V
Peripheral mode with High speed IO
24 MHz
f
SPI
SPI clock frequency
Clock max speed >= 64MHz
2.7 < VDD < 3.6V
Peripheral mode with High speed IO
32 MHz
DC
SCK
SCK Duty Cycle 40 50 60 %
Controller
t
SCLK_H/L
SCLK High or Low time
(tSPI/2) -
1
tSPI / 2
(tSPI/2) +
1
ns
t
SU.CI
POCI input data setup time
(1)
2.7 < VDD < 3.6V, delayed sampling
enabled
1 ns
t
SU.CI
POCI input data setup time
(1)
1.62 < VDD < 2.7V, delayed sampling
enabled
1 ns
t
SU.CI
POCI input data setup time
(1)
2.7 < VDD < 3.6V, no delayed sampling 27 ns
t
SU.CI
POCI input data setup time
(1)
1.62 < VDD < 2.7V, no delayed sampling 35 ns
t
HD.CI
POCI input data hold time 9 ns
t
VALID.CO
PICO output data valid time
(2)
10 ns
MSPM0G3507, MSPM0G3506, MSPM0G3505
SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
www.ti.com
48 Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: MSPM0G3507 MSPM0G3506 MSPM0G3505
To Next Page
Loading...
Need help?
General
