Texas Instruments MSPM0G3507 - User Manual

MSPM0G350x Mixed-Signal Microcontrollers With CAN-FD Interface
1 Features
• Core
– Arm
®
32-bit Cortex
®
-M0+ CPU with memory
protection unit, frequency up to 80 MHz
• Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62 V to 3.6 V
• Memories
– Up to 128KB of flash memory with error
correction code (ECC)
– Up to 32KB of ECC protected SRAM with
hardware parity
• High-performance analog peripherals
– Two simultaneous sampling 12-bit 4-Msps
analog-to-digital converters (ADCs) with up to
17 external channels
• 14-bit effective resolution at 250-ksps with
hardware averaging
– One 12-bit 1-MSPS digital-to-analog converter
with integrated output buffer (DAC)
– Two zero-drift zero-crossover chopper op-amps
(OPA)
• 0.5-µV/°C drift with chopping
• Integrated programmable gain stage, up to
32x
– One general-purpose amplifier (GPAMP)
– Three high-speed comparators (COMP) with 8-
bit reference DACs
• 32-ns propagation delay in high-speed
mode
• Support low-power mode operation down to
<1 µA
– Programmable analog connections between
ADC, OPAs, COMP and DAC
– Configurable 1.4-V or 2.5-V internal shared
voltage reference (VREF)
– Integrated temperature sensor
• Optimized low-power modes
– RUN: 96 µA/MHz (CoreMark)
– SLEEP: 458 µA at 4 MHz
– STOP: 47 µA at 32 kHz
– STANDBY: 1.5 µA with RTC and SRAM
retention
– SHUTDOWN: 78 nA with IO wake-up capability
• Intelligent digital peripherals
– 7-channel DMA controller
– Math accelerator supports DIV, SQRT, MAC
and TRIG computations
– Seven timers supports up to 22 PWM channels
• One 16-bit general-purpose timer
• One 16-bit general-purpose timer supports
QEI
• Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
• One 32-bit high-resolution general-purpose
timer
• Two 16-bit advanced timers with deadband
support up to 12 PWM channels
– Two window-watchdog timers
– RTC with alarm and calendar mode
• Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
– Two I
2
C interfaces support up to FM+ (1
Mbit/s), SMBus/PMBus, and wakeup from
STOP mode
– Two SPIs, one SPI supports up to 32 Mbits/s
– One Controller Area Network (CAN) interface
supports CAN 2.0 A or B and CAN-FD
• Clock system
– Internal 4- to 32-MHz oscillator with up to
±1.2% accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80 MHz
– Internal 32-kHz low-frequency oscillator
(LFOSC) with ±3% accuracy
– External 4- to 48-MHz crystal oscillator (HFXT)
– External 32-kHz crystal oscillator(LFXT)
– External clock input
• Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
– True random number generator (TRNG)
– AES encryption with 128 or 256-bit key
• Flexible I/O features
– Up to 60 GPIOs
• Two 5-V tolerant IOs
• Two high-drive IOs with 20-mA drive
strength
• Development support
– 2-pin serial wire debug (SWD)
• Package options
– 64-pin LQFP
– 48-pin LQFP, VQFN
– 32-pin VQFN
– 28-pin VSSOP
• Family members (also see Device Comparison)
– MSPM0G3505: 32KB flash, 16KB RAM
– MSPM0G3506: 64KB flash, 32KB RAM
– MSPM0G3507: 128KB flash, 32KB RAM
ADVANCE INFORMATION
MSPM0G3507, MSPM0G3506, MSPM0G3505
SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.

Texas Instruments MSPM0G3507 Specifications

General

Microcontroller Series	MSPM0
Core	Arm Cortex-M0+
Flash Memory	128 KB
Max Clock Frequency	80 MHz
Communication Interfaces	UART, SPI, I2C
Package Type	LQFP
Operating Voltage	1.62 V to 3.63 V

Summary

1 Features

Core and Operating Characteristics

Details on the CPU core, frequency, and operating voltage/temperature range.

Memory and Analog Peripherals

Information on flash/SRAM, ADCs, DAC, op-amps, and amplifiers.

Digital and System Features

Covers timers, communication interfaces, clock system, and security features.

Support and Package Information

Includes development tools, package types, and family member variants.

2 Applications

3 Description

4 Functional Block Diagram

5 Device Comparison

6 Pin Configuration and Functions

6.1 Pin Diagrams

Visual representations of pin assignments for different package types.

6.2 Pin Attributes

Table describing the function and availability of each pin across packages.

6.3 Signal Descriptions

Detailed descriptions of all available peripheral signals and their pin mappings.

6.4 Connections for Unused Pins

Guidance on proper termination for unused device pins.

7 Specifications

7.1 Absolute Maximum Ratings

Defines the stress limits beyond which device damage may occur.

7.2 ESD Ratings

Specifies electrostatic discharge protection levels for device handling.

7.3 Recommended Operating Conditions

Defines the voltage, temperature, and frequency ranges for reliable operation.

7.4 Thermal Information

7.5 Supply Current Characteristics

7.5.1 RUN;SLEEP Modes

Supply current data for RUN and SLEEP modes at different MCLK frequencies.

7.5.2 STOP;STANDBY Modes

Supply current data for STOP and STANDBY modes at different ULPCLK frequencies.

7.6 Power Supply Sequencing

7.6.1 POR and BOR

Details on POR and BOR voltage levels, hysteresis, and delay parameters.

7.7 Flash Memory Characteristics

7.8 Timing Characteristics

7.9 Clock Specifications

7.9.1 System Oscillator (SYSOSC)

Parameters and accuracy for the internal system oscillator.

7.9.2 Low Frequency Oscillator (LFOSC)

Specifications for the low-frequency internal oscillator.

7.9.3 System Phase Lock Loop (SYSPLL)

Characteristics of the phase-locked loop for frequency synthesis.

7.9.5 High Frequency Crystal;Clock

7.10 Digital IO

7.10.1 Electrical Characteristics

Defines voltage levels, hysteresis, and leakage for digital I/O.

7.10.2 Switching Characteristics

Specifies output frequency and rise/fall times for digital I/O.

7.11 Analog Mux VBOOST

7.12 ADC

7.12.1 Electrical Characteristics

Defines ADC input voltage, resolution, current, and reference parameters.

7.13 Temperature Sensor

7.14 VREF

7.14.1 Voltage Characterisitcs

Details minimum supply voltage and output voltage characteristics for VREF.

7.15 Comparator (COMP)

7.15.1 Comparator Electrical Characteristics

Defines input range, hysteresis, delay, and current for comparators.

7.16 DAC

7.16.1 DAC_Supply Specifications

Specifies voltage and current requirements for the DAC.

7.17 GPAMP

7.17.1 Electrical Characteristics

Defines common mode range, gain, noise, and slew rate for GPAMP.

7.17.2 Switching Characteristics

Specifies enable, disable, and settling times for the GPAMP.

7.18 OPA

7.18.1 Electrical Characteristics

Defines common mode range, quiescent current, and noise for OPAs.

7.18.2 Switching Characteristics

Specifies enable, disable, and settling times for the OPAs.

7.18.3 PGA Mode

Provides gain characteristics and resistance values for the programmable gain amplifier.

7.19 I2 C

7.19.1 I2 C Characteristics

Defines clock frequency, hold times, and setup times for I2C communication.

7.19.2 I2 C Filter

Specifies parameters for the input filter used to suppress spikes in I2C signals.

7.20 SPI

7.20.1 SPI

Defines SPI clock frequency, duty cycle, and data timing parameters.

7.20.2 SPI Timing Diagram

Illustrates timing for SPI communication in controller mode.

7.21 UART

7.22 TIMx

7.23 TRNG

7.23.1 TRNG Electrical Characteristics

Specifies current consumption for the TRNG module.

7.24 Emulation and Debug

7.24.1 SWD Timing

Defines the clock frequency for the SWD debug interface.

8 Detailed Description

8.1 CPU

Describes the ARM Cortex-M0+ CPU core, its features, and sub-systems.

8.2 Operating Modes

Explains the five device operating modes for power optimization.

8.3 Power Management Unit (PMU)

Details the PMU's role in supply monitoring and power management.

8.5 DMA

8.7 Memory

8.7.1 Memory Organization

Details the address ranges for code, SRAM, and peripheral memory regions.

8.10 GPIO

8.12 ADC

8.15 COMP

8.16 DAC

8.24 I2 C

8.25 SPI

8.32 Serial Wire Debug Interface

8.33 Boot Strap Loader (BSL)

8.35 Identification

9 Applications, Implementation, and Layout

9.1 Typical Application

Shows a basic application schematic with recommended external components.

10 Device and Documentation Support

10.1 Getting Started and Next Steps

Guides for beginning development with MSPM0 MCUs.

10.2 Device Nomenclature

Explains the naming convention used for MSP MCU devices.

10.3 Tools and Software

Lists available development tools, IDEs, and software kits.

10.4 Documentation Support

10.5 Support Resources

10.7 Electrostatic Discharge Caution

11 Mechanical, Packaging, and Orderable Information

12 Revision History