6.2 Pin Attributes
The following table describes the functions available on every pin for each device package.
Note
Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that
lets users configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1. Pin Attributes
PINCMx
PIN
NAME
SIGNAL NAMES PIN NUMBER
IO
STRUCTU
RE
ANALOG DIGITAL [PIN FUNCTION]
(1)
64 LQFP
48 LQFP, VQFN
32 VQFN
28 VSSOP
N/A VDD 40 6 4 7 Power
N/A VSS 41 7 5 8 Power
N/A VCORE 32 48 32 3 Power
N/A NRST 38 4 3 6 Reset
1
PA0 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C0 [4] / TIMA_FAL1
[5] / TIMG8_C1 [6] / FCC_IN [7]
33 1 1 4
5V Tol.
Open-Drain
2
PA1 UART0_RX [2] / I2C0_SCL [3] / TIMA0_C1 [4] / TIMA_FAL2
[5] / TIMG8_IDX [6] / TIMG8_C0 [7]
34 2 2 5
5V Tol.
Open-Drain
3
PA28 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C3 [4] / TIMA_FAL0
[5] / TIMG7_C0 [6] / TIMA1_C0 [ 7]
35 3 – – High-Drive
4
PA29 I2C1_SCL [2] / UART2_RTS [3] / TIMG8_C0 [4] /
TIMG6_C0 [5]
36 – – – Standard
5
PA30 I2C1_SDA [2] / UART2_CTS [3] / TIMG8_C1 [4] /
TIMG6_C1 [5]
37 – – – Standard
6
PA31 UART0_RX [2] / I2C0_SCL [3] / TIMA0_C3N [4] /
TIMG12_C1 [5] / CLK_OUT [6]/ TIMG7_C1 [7] / TIMA1_C1
[8]
39 5 – – High-Drive
7
PA2
ROSC
TIMG8_C1 [2] / SPI0_CS0 [3] / TIMG7_C1 [4] / SPI1_CS0
[5]
42 8 6 9 Standard
8
PA3
LFXIN
TIMG8_C0 [2] / SPI0_CS1 [3] / UART2_CTS [4] /
TIMA0_C2 [5] / COMP1_OUT [6] / TIMG7_C0 [7] /
TIMA0_C1 [8] / I2C1_SDA [9]
43 9 7 10 Standard
9
PA4
LFXOUT
TIMG8_C1 [2] / SPI0_POCI [3] / UART2_RTS [4] /
TIMA0_C3 [5] / LFCLK_IN [6] / TIMG7_C1 [7] / TIMA0_C1N
[8] / I2C1_SCL [9]
44 10 8 11 Standard
10
PA5
HFXIN
TIMG8_C0 [2] / SPI0_PICO [3] / TIMA_FAL1 [4] /
TIMG0_C0 [5] / TIMG6_C0 [6] / FCC_IN [7]
45 11 9 12 Standard
11
PA6
HFXOUT
TIMG8_C1 [2] / SPI0_SCK [3] / TIMA_FAL0 [4] / TIMG0_C1
[5] / HFCLK_IN [6] / TIMG6_C1 [ 7] / TIMA0_C2N [8]
46 12 10 13 Standard
12
PB0 UART0_TX [2] / SPI1_CS2 [3] / TIMA1_C0 [4] / TIMA0_C2
[5]
47 – – – Standard
13
PB1 UART0_RX [2] / SPI1_CS3 [3] / TIMA1_C1 [4] /
TIMA0_C2N [5]
48 – – – Standard
14
PA7 COMP0_OUT [2] / CLK_OUT [3] / TIMG8_C0 [4] /
TIMA0_C2 [5] / TIMG8_IDX [6] / TIMG7_C1 [7] / TIMA0_C1
[8]
49 13 11 – Standard
15
PB2 UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] /
TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] /
TIMA1_C0 [8]
50 14 – – Standard
MSPM0G3507, MSPM0G3506, MSPM0G3505
SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
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